James Che-Jen Yu

US Patent:

6403500, Jun 11, 2002

Filed:

Jan 12, 2001

Appl. No.:

09/760241

Inventors:

James Jiahua Yu - Milpitas CA
Kouros Ghandehari - Santa Clara CA
Bhanwar Singh - Morgan Hill CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2131

US Classification:

438782, 438778, 438780, 427 96, 427240

Abstract:

An exemplary method of depositing photoresist material on an integrated circuit wafer is described. This method can include providing a cross-shaped resist dispenser including a plurality of resist dispense nozzles; dispensing photoresist material through the plurality of resist dispense nozzles to an integrated circuit wafer; and rotating at least one of the cross-shaped resist dispenser and the integrated circuit wafer.

US Patent:

6514874, Feb 4, 2003

Filed:

Jun 6, 2001

Appl. No.:

09/875635

Inventors:

James Jiahua Yu - Milpitas CA
Bhanwar Singh - Morgan Hill CA
Angela T. Hui - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21461

US Classification:

438744, 438672, 438735

Abstract:

A method of fabricating an integrated circuit can include providing a layer of silicon nitride over a semiconductor substrate where the layer of silicon nitride has a first thickness selected based on a desired size of extensions; providing a layer of photoresist material over the layer of silicon nitride; patterning the layer of photoresist to form photoresist features being separated at the top of the photoresist features by one minimum lithographic feature and etching a portion of the layer of silicon nitride to form a hole for an integrated circuit device feature. The photoresist features include extensions at the bottom of the photoresist features. The extensions define footings. These footings reduce the separation at the bottom of the photoresist features. As such, exposed portions of the layer of silicon nitride are less than one minimum lithographic feature in width.

US Patent:

6592939, Jul 15, 2003

Filed:

Jun 6, 2001

Appl. No.:

09/875596

Inventors:

James Jiahua Yu - Milpitas CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

B05D 312

US Classification:

427240, 427402, 4274071, 427425, 118 52, 118320, 438758

Abstract:

An exemplary method of using developer as a solvent to spread photoresist faster and reduce photoresist consumption can include dispensing a developer solution onto an integrated circuit wafer, spinning the integrated circuit wafer to distribute the developer solution over the integrated circuit wafer, and dispensing a photoresist solution onto the integrated circuit covered with the developer solution.

US Patent:

7289498, Oct 30, 2007

Filed:

Jun 28, 2002

Appl. No.:

10/187239

Inventors:

James Yu - San Jose CA, US
Mike Morrison - Sunnyvale CA, US
John Rigby - Reading, GB

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H04L 12/28

US Classification:

370389, 711108

Abstract:

A technique for classifying traffic at a network node involves programming a content addressable memory (CAM) array with multiple class-specific entries, where each of the class-specific entries has an associated traffic class, obtaining a protocol-independent key field from an incoming packet, and searching the programmed CAM array with the protocol-independent key field to identify an associated traffic class of the incoming packet. In another embodiment, each of the class-specific entries has an associated traffic distribution policy, which may be applied to an incoming packet.

US Patent:

7333468, Feb 19, 2008

Filed:

May 16, 2005

Appl. No.:

11/129798

Inventors:

Sebastian Turullols - Los Altos CA, US
Aly E. Orady - Sunnyvale CA, US
James J. Yu - San Jose CA, US
Andrew C. Yang - Sunnyvale CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H04J 3/24
H04J 3/06
H04L 12/56
H04L 7/00
H04L 7/04
H04L 9/00
H04B 1/18
H04B 1/10

US Classification:

370349, 370350, 37039562, 370509, 370514, 4551803, 4551811, 4551832, 375357, 375366, 375362, 375350, 375355, 713178

Abstract:

A packet stream multiplexer may include one or more control loops (e. g. , digital phase locked loops) for tracking the source clock frequency associated with a packet stream. A first control loop may slowly drive an error between a received timestamp and an estimated timestamp to zero. A second control loop may more quickly drive a first derivative of the error to zero. The second control loop may include a set of digital filters ordered according to tracking speed. The output of the slowest filter is initially selected for updating the source clock frequency estimate. As time progresses, the faster filters are selected in succession. The estimated source clock frequency is used to restamp packets of the packet stream as they are sent out onto an output channel.

US Patent:

7696765, Apr 13, 2010

Filed:

Sep 3, 2007

Appl. No.:

11/849336

Inventors:

James Yu - San Jose CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G01R 27/02
G06F 1/26

US Classification:

324722, 324713, 713300

Abstract:

A system and method for measuring a cable resistance in a power over Ethernet (PoE) application. A short circuit module in a powered device is designed to produce a short circuit effect upon receipt of a cable resistance detection voltage. The cable resistance detection voltage can be designed to be greater than a voltage for detection or classification and less than a voltage for powering of the powered device. The measurement of the current at a time when a short circuit effect is produced at the powered device enables a calculation of the actual resistance of the cable on a given PoE port.

US Patent:

7738498, Jun 15, 2010

Filed:

Aug 9, 2005

Appl. No.:

11/199627

Inventors:

James J. Yu - San Jose CA, US
Andrew C. Yang - Sunnyvale CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H04J 3/06

US Classification:

370503, 375376, 375215

Abstract:

A system including a memory (storing a set of data records), a digital phase-locked loop (PLL) and digital circuitry. Each of the data records is allocated to one packet stream in a set of packet streams. The digital circuitry is configured to: invoke a read operation from the memory in response to a received stream indicator and received channel indicator corresponding to a current timestamp-bearing packet; generate an output timestamp for the current packet equal to an expected timestamp provided by the memory as part of the read operation; and generate error data based on argument data including a received input timestamp, a received slot delay value, a previous source frequency estimate and an expected timestamp provided as part of the read operation. The digital PLL is configured to compute an updated source frequency estimate based on information including the error data and the previous source frequency estimate.

US Patent:

7764717, Jul 27, 2010

Filed:

May 6, 2005

Appl. No.:

11/123820

Inventors:

James J. Yu - San Jose CA, US
Sebastian Turullols - Los Altos CA, US
Aly E. Orady - Sunnyvale CA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

H04J 3/02

US Classification:

370537, 370271

Abstract:

A multiplexing system having an input unit, a storage unit and control unit. The input unit receives data units corresponding to multiple source data streams and extracts packets from the data units. The control unit computes data rate estimates for the source data streams based on timestamps in the source data streams. The storage unit stores a packet count and previous timestamp value for each source data stream. The control unit computes a preliminary data rate estimate for a source data stream based on samples of a local clock if timestamps are not received promptly. The control unit also computes scheduling rates based on the data rate estimates. The scheduling rates are used to control the rates of allocation of data from the source data streams into a multiplexed output stream. The control unit computes scheduling rates in a way that avoids oversubscription of the output channel.