Jamil J Kawa

US Patent:

6369619, Apr 9, 2002

Filed:

Jul 14, 2000

Appl. No.:

09/615959

Inventors:

Jamil Kawa - Santa Clara CA
Rahul Nimaiyar - Cupertino CA
Puneet Sawhney - San Jose CA
Anwar Awad - Sunnyvale CA

Assignee:

Artisan Components, Inc. - Sunnyvale CA

International Classification:

G05F 110

US Classification:

327108, 327535

Abstract:

The present invention provides a voltage tolerant input/output circuit configured to ensure proper interface tolerance between various close voltages in deep sub-micron circuits without any DC leakage. The voltage tolerant input/output circuit includes (1) an arbiter circuit logically configured to ensure that a gate of a P-driver of the voltage tolerant input/output circuit is biased at the higher of an input/output voltage and an input/output supply voltage when the P-driver is tri-stated, (2) a bias circuit logically configured to biased a floating N-well of the P-driver to ensure that no parasitic diodes formed between any source or drain of a p-device of the voltage tolerant input/output circuit and the N-well of the P-driver is forward biased, and (3) a driver circuit comprising the P-driver.

US Patent:

7100142, Aug 29, 2006

Filed:

Apr 7, 2004

Appl. No.:

10/820523

Inventors:

Jamil Kawa - Campbell CA, US
Narendra V. Shenoy - Bangalore, IN
Raul Camposano - Los Altos CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 17, 716 18, 716 16, 716 3, 716 2

Abstract:

One embodiment of the invention provides a system for creating a mask-programmable module from standard cells. The system operates by first specifying characteristics of an end design and then selecting a plurality of standard cells from a standard cell library based on the characteristics of the end design. Next, the system combines the plurality of standard cells into a mask-programmable module, wherein instances of the mask-programmable module are repeated to form a mask-programmable fabric. The system also designs a mask-programmable interconnect to match the mask-programmable module, whereby connections within the mask-programmable module and between mask-programmable modules can be generated by programming the mask-programmable interconnect.

US Patent:

7260807, Aug 21, 2007

Filed:

Dec 12, 2003

Appl. No.:

10/734399

Inventors:

Narendra V. Shenoy - Bangalore, IN
Jamil Kawa - Campbell CA, US
Raul Camposano - Los Altos CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 18, 716 3, 716 17, 716 19

Abstract:

One embodiment of the invention provides a system that facilitates designing an integrated circuit using a mask-programmable fabric, which contains both mask-programmable logic and a mask-programmable interconnect. During operation, the system receives a description of a mask-programmable cell, wherein instances of the mask-programmable cell are repeated to form the mask-programmable fabric. The system uses this description of the mask-programmable cell to generate a derived library containing cells that can be obtained by programming the mask-programmable cell. Next, the system receives a high-level design for the integrated circuit. The system then performs a synthesis operation on the high-level design to generate a preliminary netlist for the high-level design, wherein the preliminary netlist contains references to cells in the derived library. Finally, the system converts the preliminary netlist into a netlist that contains references to the mask-programmable cell with the logic appropriately programmed. The netlist is then placed and routed with the mask programmable constraints on the mask programmable fabric.

US Patent:

7417451, Aug 26, 2008

Filed:

Oct 7, 2005

Appl. No.:

11/245933

Inventors:

Jamil Kawa - Campbell CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

H03K 17/16

US Classification:

326 27, 326 82, 326 33

Abstract:

A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the logic block can retain state information while still greatly reducing sub-threshold leakage current.

US Patent:

7594213, Sep 22, 2009

Filed:

Nov 24, 2004

Appl. No.:

10/997396

Inventors:

Xin Wang - Pasadena CA, US
Charles C. Chiang - San Jose CA, US
Jamil Kawa - Campbell CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 10, 716 2, 716 4, 716 19, 716 21

Abstract:

One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add dummy features to a layout to reduce the post-CMP topography variation. During operation, the system discretizes a layout of an integrated circuit into a plurality of panels. Next, the system computes a feature density and a slack density for the plurality of panels. The system then computes a dummy feature density for the plurality of panels by, iteratively, (a) calculating an effective feature density for the plurality of panels using the feature density and a function that models the CMP process, (b) calculating a filling amount for a set of panels in the plurality of panels using a target feature density, the effective feature density, and the slack density, and (c) updating the feature density, the slack density, and the dummy feature density for the set of panels using the filling amount. In one embodiment of the present invention, the iterative process is guided by a variance-minimizing heuristic to efficiently select the set of panels and assign/remove dummy density to the set of panels to decrease the effective feature density variation.

US Patent:

7679872, Mar 16, 2010

Filed:

Jul 21, 2008

Appl. No.:

12/176801

Inventors:

Jamil Kawa - Campbell CA, US
Subarnarekha Sinha - Menlo Park CA, US
Min-Chun Tsai - San Jose CA, US
ZongWu Tang - Pleasanton CA, US
Qing Su - Sunnyvale CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

H02H 9/04
H02H 9/00

US Classification:

361 56

Abstract:

Embodiments of an interface circuit are described. This interface circuit includes an input pad, a control node and a transistor, which has three terminals. A first terminal is electrically coupled to the input pad and a second terminal is electrically coupled to the control node. Moreover, the interface circuit includes a micro-electromechanical system (MEMS) switch, which is electrically coupled to the input pad and the control node, where the MEMS switch is in parallel with the transistor. In the absence of a voltage applied to a control terminal of the MEMS switch, the MEMS switch is closed, thereby electrically coupling the input pad and the control node. Furthermore, when the voltage is applied to the control terminal of the MEMS switch, the MEMS switch is open, thereby electrically decoupling the input pad and the control node.

US Patent:

7795906, Sep 14, 2010

Filed:

Jul 24, 2008

Appl. No.:

12/179555

Inventors:

Jamil Kawa - Campbell CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

H03K 19/003

US Classification:

326 33, 326 27

Abstract:

A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the logic block can retain state information while still greatly reducing sub-threshold leakage current.

US Patent:

8176456, May 8, 2012

Filed:

Dec 24, 2008

Appl. No.:

12/343958

Inventors:

Xin Wang - Pasadena CA, US
Charles C. Chiang - San Jose CA, US
Jamil Kawa - Campbell CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716119, 716 54, 716118

Abstract:

One embodiment of the present invention provides a system that computes dummy feature density for a CMP (Chemical-Mechanical Polishing) process. Note that the dummy feature density is used to add dummy features to a layout to reduce the post-CMP topography variation. During operation, the system discretizes a layout of an integrated circuit into a plurality of panels. Next, the system computes a feature density and a slack density for the plurality of panels. The system then computes a dummy feature density for the plurality of panels by, iteratively, (a) calculating an effective feature density for the plurality of panels using the feature density and a function that models the CMP process, (b) calculating a filling amount for a set of panels in the plurality of panels using a target feature density, the effective feature density, and the slack density, and (c) updating the feature density, the slack density, and the dummy feature density for the set of panels using the filling amount. In one embodiment of the present invention, the iterative process is guided by a variance-minimizing heuristic to efficiently select the set of panels and assign/remove dummy density to the set of panels to decrease the effective feature density variation.