Janet L Olson

US Patent:

59034769, May 11, 1999

Filed:

Oct 29, 1996

Appl. No.:

8/739219

Inventors:

Ashutosh S. Mauskar - Sunnyvale CA
Janet Olson - Saratoga CA
James Sproch - Saratoga CA
Yueqin Lin - Sunnyvale CA
Ivailo Nedelchev - Santa Clara CA

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F17/50

US Classification:

364578

Abstract:

A system and method for modeling power consumed by a logic cell in a estimation process over an integrated circuit, represented by logic cells and connections between cells, using a three dimensional power modeling table (3-D power table). The 3-D power table utilizes dual output capacitance indices and a single input transition time (which can be a weighted average input transition time) index. Each 3-D power table of the present invention includes a set of index reference points for the first output capacitance index, a set of index reference points for the second output capacitance index, a set of index reference points for the input transition time, and a set of power reference points that correspond to the above index reference points. For a given set of values input for: (1) the first output capacitance index; (2) the second output capacitance index; and (3) the input transition time index, linear interpolation is performed across the three indices to arrive at the given output power consumption value. The 3-D power tables are used to accurately model the power consumed by a cell having two outputs which are functionally equal or opposite, for instance, a flip-flop with Q and Q' outputs.

US Patent:

61956309, Feb 27, 2001

Filed:

May 10, 1999

Appl. No.:

9/309485

Inventors:

Ashutosh S. Mauskar - Sunnyvale CA
Janet Olson - Saratoga CA
James Sproch - Saratoga CA
Yueqin Lin - Sunnyvale CA
Ivailo Nedelchev - Santa Clara CA

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 1750

US Classification:

703 18

Abstract:

A system and method for modeling power consumed by a logic cell in a estimation process over an integrated circuit, represented by logic cells and connections between cells, using a three dimensional power modeling table (3-D power table). The 3-D power table utilizes dual output capacitance indices and a single input transition time (which can be a weighted average input transition time) index. Each 3-D power table of the present invention includes a set of index reference points for the first output capacitance index, a set of index reference points for the second output capacitance index, a set of index reference points for the input transition time, and a set of power reference points that correspond to the above index reference points. For a given set of values input for: (1) the first output capacitance index; (2) the second output capacitance index; and (3) the input transition time index, linear interpolation is performed across the three indices to arrive at the given output power consumption value. The 3-D power tables are used to accurately model the power consumed by a cell having two outputs which are functionally equal or opposite, for instance, a flip-flop with Q and Q' outputs.

US Patent:

20180107777, Apr 19, 2018

Filed:

Oct 17, 2016

Appl. No.:

15/295837

Inventors:

- Mountain View CA, US
Jovanka Ciric Vujkovic - Mountain View CA, US
Van E. Morgan - Phoenixville PA, US
Janet L. Olson - Saratoga CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

Abstract:

Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiment can perform enumeration on a hardware description language (HDL) description of an IC design to obtain a enumerated IC design that includes at least one technology-independent wide-gate or technology-independent wide-bus, wherein the technology-independent wide-gate represents a logical function that is performed on a variable number of inputs, and wherein the technology-independent wide-bus represents a variable number of signals that are part of a bus. The embodiments can then perform technology-independent IC optimization, synthesis, and technology-dependent IC optimization to obtain an optimized and synthesized IC design.