Janet R Olson

US Patent:

6480815, Nov 12, 2002

Filed:

May 10, 1999

Appl. No.:

09/309479

Inventors:

Janet Olson - Saratoga CA
James Sproch - Saratoga CA
Yueqin Lin - Sunnyvale CA
Ivailo Nedelchev - Santa Clara CA
Ashutosh S. Mauskar - Sunnyvale CA

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 1750

US Classification:

703 14, 703 18, 703 20, 716 17, 716 18

Abstract:

A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell âlibraryâ within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e. g. , input pin) caused the designated pin to transition.

US Patent:

59034769, May 11, 1999

Filed:

Oct 29, 1996

Appl. No.:

8/739219

Inventors:

Ashutosh S. Mauskar - Sunnyvale CA
Janet Olson - Saratoga CA
James Sproch - Saratoga CA
Yueqin Lin - Sunnyvale CA
Ivailo Nedelchev - Santa Clara CA

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F17/50

US Classification:

364578

Abstract:

A system and method for modeling power consumed by a logic cell in a estimation process over an integrated circuit, represented by logic cells and connections between cells, using a three dimensional power modeling table (3-D power table). The 3-D power table utilizes dual output capacitance indices and a single input transition time (which can be a weighted average input transition time) index. Each 3-D power table of the present invention includes a set of index reference points for the first output capacitance index, a set of index reference points for the second output capacitance index, a set of index reference points for the input transition time, and a set of power reference points that correspond to the above index reference points. For a given set of values input for: (1) the first output capacitance index; (2) the second output capacitance index; and (3) the input transition time index, linear interpolation is performed across the three indices to arrive at the given output power consumption value. The 3-D power tables are used to accurately model the power consumed by a cell having two outputs which are functionally equal or opposite, for instance, a flip-flop with Q and Q' outputs.

US Patent:

61956309, Feb 27, 2001

Filed:

May 10, 1999

Appl. No.:

9/309485

Inventors:

Ashutosh S. Mauskar - Sunnyvale CA
Janet Olson - Saratoga CA
James Sproch - Saratoga CA
Yueqin Lin - Sunnyvale CA
Ivailo Nedelchev - Santa Clara CA

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 1750

US Classification:

703 18

Abstract:

A system and method for modeling power consumed by a logic cell in a estimation process over an integrated circuit, represented by logic cells and connections between cells, using a three dimensional power modeling table (3-D power table). The 3-D power table utilizes dual output capacitance indices and a single input transition time (which can be a weighted average input transition time) index. Each 3-D power table of the present invention includes a set of index reference points for the first output capacitance index, a set of index reference points for the second output capacitance index, a set of index reference points for the input transition time, and a set of power reference points that correspond to the above index reference points. For a given set of values input for: (1) the first output capacitance index; (2) the second output capacitance index; and (3) the input transition time index, linear interpolation is performed across the three indices to arrive at the given output power consumption value. The 3-D power tables are used to accurately model the power consumed by a cell having two outputs which are functionally equal or opposite, for instance, a flip-flop with Q and Q' outputs.

US Patent:

59496894, Sep 7, 1999

Filed:

Oct 29, 1996

Appl. No.:

8/739311

Inventors:

Janet Olson - Saratoga CA
James Sproch - Saratoga CA
Yueqin Danny Lin - Sunnyvale CA
Ivailo Nedelchev - Santa Clara CA
Ashutosh S. Mauskar - Sunnyvale CA

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 1750

US Classification:

364488

Abstract:

A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell "library" within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e. g. , input pin) caused the designated pin to transition.

US Patent:

58385797, Nov 17, 1998

Filed:

Oct 29, 1996

Appl. No.:

8/740502

Inventors:

Janet Olson - Saratoga CA
Ivailo Nedelchev - Santa Clara CA
Yuegin Danny Lin - Sunnyvale CA
Ashutosh S. Mauskar - Sunnyvale CA
James Sproch - Saratoga CA

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 1750

US Classification:

364488

Abstract:

A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular pin (e. g. , input, output, bidirectional, internal) based on a prescribed condition of the state of signals that exist contemporaneously with a signal transition on the particular pin. This is referred to as state dependent power modeling. A different power consumption value can be provided for each different modeled state. The logic cells and the power consumption model for them are stored in a logic cell "library" within the computer system. State dependent power modeling of the present invention allows library designers to specify a different set of power values depending on the condition of one or more pins of the library cell (e. g. , the library's representation of the logic cell).

US Patent:

20180246996, Aug 30, 2018

Filed:

Feb 28, 2017

Appl. No.:

15/445689

Inventors:

- Mountain View CA, US
Janet L. Olson - Saratoga CA, US
Mukund Sivaraman - Palo Alto CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

Abstract:

Systems and techniques are described for producing a synthesized IC design that includes design-for-testability (DFT) circuitry. A register-transfer-level (RTL) representation of an IC design can be received, wherein the RTL representation includes functional logic. Next, DFT logic can be added to the RTL representation, and DFT placement guidance for placing the DFT logic can be generated. Synthesis can be performed on the RTL representation to obtain the synthesized IC design, wherein during synthesis, (1) the functional logic and the DFT logic can be placed, wherein the DFT logic is placed based on the DFT placement guidance, (2) scan chains can be inserted and placed, and (3) the DFT logic can be electrically connected with the scan chains.

US Patent:

20180107777, Apr 19, 2018

Filed:

Oct 17, 2016

Appl. No.:

15/295837

Inventors:

- Mountain View CA, US
Jovanka Ciric Vujkovic - Mountain View CA, US
Van E. Morgan - Phoenixville PA, US
Janet L. Olson - Saratoga CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

Abstract:

Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiment can perform enumeration on a hardware description language (HDL) description of an IC design to obtain a enumerated IC design that includes at least one technology-independent wide-gate or technology-independent wide-bus, wherein the technology-independent wide-gate represents a logical function that is performed on a variable number of inputs, and wherein the technology-independent wide-bus represents a variable number of signals that are part of a bus. The embodiments can then perform technology-independent IC optimization, synthesis, and technology-dependent IC optimization to obtain an optimized and synthesized IC design.