Jared C Anderson

US Patent:

44307110, Feb 7, 1984

Filed:

Apr 7, 1983

Appl. No.:

6/482818

Inventors:

Jared A. Anderson - Woodside CA
Robert V. Van Gelder - Berkeley CA
Lauren F. Yazolino - Oakland CA
Jimmy E. Braun - Orange CA

Assignee:

Signetics Corporation - Sunnyvale CA

International Classification:

G06F 926

US Classification:

364200

Abstract:

A central processing unit capable of executing the IBM System/370 Universal Instruction Set is disclosed. The instruction set establishes the functional specifications for the processing unit, features of which include: 8-bit (byte) alphanumeric coding, 4-bit packed decimal coding (2 digits per byte), two's complement fixed-point binary arithmetic, two levels of indexing, sixteen 32-bit (4 byte) addressable general registers, four 64-bit floating point registers, and program status word and control registers. Principal features of the hardware architecture include the use of a single main data/instruction bus, transfers to and from the main bus being made under encoded microprogram control, and placement of the fixed-point binary arithmetic logic unit elements and the associated sixteen general registers on a single cascaded group of LSIC chips which operate under control of the microcode. The microcode store is addressed by a microprogram control unit which includes a control counter stack memory and a return address stack memory permitting up to sixteen levels of microprogram sub-routines to be used.

US Patent:

43522742, Oct 5, 1982

Filed:

Jun 2, 1980

Appl. No.:

6/155695

Inventors:

Jared A. Anderson - Woodside CA
Robert V. Van Gelder - Berkeley CA
Lauren F. Yazolino - Oakland CA
Jimmy E. Braun - Orange CA

Assignee:

Signetics Corporation - Sunnyvale CA

International Classification:

F25B 100
F25D 1704

US Classification:

62229

Abstract:

A cabinet for a central processing unit, made up of a card cage and refrigeration unit, for mounting and cooling electronic components on a group of vertically-aligned, closely-spaced circuit boards. A source of recirculating, forced, refrigerated air is employed to remove the heat from the highly concentrated electronic components. For ease of maintenance, the refrigeration unit and the power supply unit take the form of independently removable modules, and the removable circuit boards are mounted in a readily accessable card cage which incorporates formed card guides which facilitate card removal and insertion.

US Patent:

43968066, Aug 2, 1983

Filed:

Oct 20, 1980

Appl. No.:

6/198677

Inventors:

Jared A. Anderson - Woodside CA

International Classification:

H04R 2500

US Classification:

179107FD

Abstract:

A general purpose hearing aid amplifier is programmably adaptable to the prescription requirements of the hearing impaired. The hearing aid amplifier comprises a bank of bandpass-restricted channels, each channel having a voltage-controlled input amplifier, a voltage-controlled compressor, and a voltage-controlled output amplifier for shaping the gain, attack and delay characteristics of the selected channel. The bank is fed through a fixed high-pass filter from a microphone input, and a mixed output drives a power amplifier for an output transducer such as a hearing aid speaker. The amplifier is programmably adaptable through the use of a monolithic programmable switch array using, for example, semiconductor fuseable link technology to preset digital-to-analog converters voltage controllable levels of the amplifiers and compressors of each channel according to a digital control input. The monolithic switch array is coupled to the programmable amplifiers through digital to analog converters which establish the programming voltages for the amplifiers and compressors. The monolithic switch array digital to analog converters may be constructed on the same monolithic semiconductor chip.

US Patent:

58910590, Apr 6, 1999

Filed:

Oct 28, 1997

Appl. No.:

8/958818

Inventors:

Jared Arnold Anderson - Woodside CA

International Classification:

A61B 5103

US Classification:

600587

Abstract:

Methods and devices are provided for detecting the presence of edema in a mammalian host. In the subject methods, the perimeter of at least one limbic extremity, preferably a lower limbic extremity such as an ankle or foot, is measured to obtain a perimeter value. The perimeter value is then compared to a control value and any difference is identified. The difference is then related to the presence of edema in the patient. The subject methods find use in the diagnosis and management of diseases characterized by the presence of edema as a physical manifestation, particularly congestive heart failure, more particularly right-sided or biventricular failure.

US Patent:

43762972, Mar 8, 1983

Filed:

Jun 2, 1980

Appl. No.:

6/155694

Inventors:

Jared A. Anderson - Woodside CA
Robert V. Van Gelder - Berkeley CA
Lauren F. Yazolino - Oakland CA
Jimmy E. Braun - Orange CA

Assignee:

Signetics Corporation - Sunnyvale CA

International Classification:

G06F 932

US Classification:

364200

Abstract:

A dynamic address translation unit for converting virtual or "logical" address values into real or "physical" address values. A translation Lookaside Buffer (TLB) stores physical addresses corresponding to a limited number of previously translated logical addresses. The available space in the TLB is divided into partitions, each of which stores address translation data for a particular user process. The TLB partition in current use is identified by the value stored in a user partition counter, which is also used to verify that certain process control information (stored in a stack memory location) associated with the partition matches the process control information for that user process which is currently in control of the central processing unit.