Jason M Breakstone

US Patent:

20120089854, Apr 12, 2012

Filed:

Oct 10, 2011

Appl. No.:

13/270084

Inventors:

Jason Breakstone - Evergreen CO, US
Alok Gupta - Oakland CA, US
Himanshu Desai - San Jose CA, US
Angelo Campos - Haledon NJ, US

Assignee:

pureSilicon Inc. - Golden CO

International Classification:

G06F 12/02
G06F 1/30

US Classification:

713323, 711102, 711E12008

Abstract:

A solid state storage device includes an interface system configured to communicate with an external host system over an aggregated multi-channel interface to receive data for storage by the solid state storage device. The solid state storage device also includes a storage processing system configured to communicate with the interface system to receive the data, process the data against storage allocation information to parallelize the data among a plurality of solid state memory subsystems, and transfer the parallelized data. The interface system is configured to receive the parallelized data, apportion the parallelized data among the plurality of solid state memory subsystems, and transfer the parallelized data for storage in the plurality of solid state memory subsystems, where each of the plurality of solid state memory subsystems is configured to receive the associated portion of the parallelized data and store the associated portion on a solid state storage medium.

US Patent:

20220214987, Jul 7, 2022

Filed:

Mar 22, 2022

Appl. No.:

17/701041

Inventors:

- Broomfield CO, US
German Kazakov - Longmont CO, US
Christopher R. Long - Colorado Springs CO, US
Jason Breakstone - Broomfield CO, US

International Classification:

G06F 13/40
G06T 1/20
G06F 13/42
G06F 12/02
G06F 9/50
G06F 13/28

Abstract:

Peer-to-peer arrangements between graphics processing units (GPUs) are provided herein. A method includes establishing synthetic devices representing GPUs in an address domain associated with a host processor, where the GPUs have a different address domain than the host processor. The method also includes forming a peer arrangement between the GPUs such that data transfers between the GPUs in the different address domain can be initiated by the host processor interfacing with the synthetic devices.

US Patent:

20220214989, Jul 7, 2022

Filed:

Mar 23, 2022

Appl. No.:

17/702057

Inventors:

- Broomfield CO, US
Christopher R. Long - Colorado Springs CO, US
Jason Breakstone - Broomfield CO, US

International Classification:

G06F 13/40
G06F 3/06
G06F 9/54

Abstract:

Emulated telemetry interfaces for host processors and management processors coupled over communication fabrics are presented herein. In one example, an apparatus includes a monitoring function executed by a host processor configured to determine telemetry related to operation of at least the host processor. A driver function executed by the host processor is configured to emulate operation of a network interface to an operating system of the host processor for transfer of communications comprising at least the telemetry to a management processor over a communication fabric different than the network interface, where the host processor and the management processor are communicatively coupled to the communication fabric.

US Patent:

20210240538, Aug 5, 2021

Filed:

Apr 19, 2021

Appl. No.:

17/233711

Inventors:

- Broomfield CO, US
James Scott Cannata - Denver CO, US
Jason Breakstone - Broomfield CO, US

Assignee:

Liqid Inc. - Broomfield CO

International Classification:

G06F 9/50
G06F 3/0482
G06F 12/02
G06F 3/0484
G06F 9/54

Abstract:

Communication fabric-coupled computing architectures, platforms, and systems are provided herein. In one example, an apparatus includes a management entity configured to establish a compute unit comprising components from among a plurality of physical computing components by at least instructing a communication fabric communicatively coupling the plurality of physical computing components to establish logical isolation within the communication fabric to form the compute unit. Responsive to an indication of a change in workload associated with at least a software component deployed to a processing element of the compute unit, the management entity is configured to adjust the logical isolation to alter a quantity of the plurality of physical computing components in the compute unit in accordance with the change in the workload.

US Patent:

20210141756, May 13, 2021

Filed:

Jan 19, 2021

Appl. No.:

17/151800

Inventors:

- Broomfield CO, US
Brenden Michael Rust - Loveland CO, US
Jason Breakstone - Broomfield CO, US
Sumit Puri - Calabasas CA, US
Bryan Schramm - Broomfield CO, US

International Classification:

G06F 13/40
H05K 7/14
H04L 12/40
H04L 12/00
G06F 13/00
G06F 13/42
H05K 1/02
H05K 1/11

Abstract:

Systems, methods, and software are disclosed herein having enhanced modular carrier form factors. In an implementation, an apparatus includes a carrier insertable into a modular bay of a chassis assembly, and a network interface card (NIC). The apparatus includes an Ethernet network cable connector configured to carry Ethernet signaling of the NIC, and a device U.2 connector configured to carry host communications of the NIC and mate with a mating U.2 connector of the modular bay when the carrier is inserted into the chassis assembly.

US Patent:

20200364172, Nov 19, 2020

Filed:

Aug 3, 2020

Appl. No.:

16/983070

Inventors:

- Broomfield CO, US
Jason Breakstone - Broomfield CO, US

Assignee:

Liqid Inc. - Broomfield CO

International Classification:

G06F 13/40
G06F 1/26
G06F 3/06
G06F 11/00
G06F 11/30
G06F 13/42
G05B 11/01

Abstract:

Systems, methods, apparatuses, and software for computing systems are provided herein. In one example, a system includes a plurality of first modules each having a Peripheral Component Interconnect Express (PCIe) interface and a processor, and a plurality of second modules each having a PCIe interface. PCIe switch circuitry is coupled to the PCIe interfaces of the first modules and the PCIe interfaces of the second modules, wherein the PCIe switch circuitry is configured to establish logical isolation in the PCIe switch circuitry between one or more first modules and one or more second modules. At least one processor instantiates access to the one or more second modules for the one or more first modules over at least the logical isolation in the PCIe switch circuitry.

US Patent:

20200264998, Aug 20, 2020

Filed:

May 4, 2020

Appl. No.:

16/866000

Inventors:

- Broomfield CO, US
James Scott Cannata - Denver CO, US
Jason Breakstone - Broomfield CO, US

Assignee:

Liqid Inc. - Broomfield CO

International Classification:

G06F 13/40
G06F 13/10
G06F 13/42
G06F 9/50

Abstract:

Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating compute units is presented that includes forming compute units among a plurality of physical computing components coupled over a Peripheral Component Interconnect Express (PCIe) fabric configured to communicatively couple the plurality of physical computing components and isolate the compute unit using logical partitioning within the PCIe fabric. The method also includes initiating a software component deployed to at least associated CPUs within the compute units, reporting telemetry to the management processor related to operation of the compute unit, and emulating operation of at least one among an Ethernet and InfiniB and interface to an operating system of the associated CPU for transfer of communications comprising at least the telemetry to the management processor over the PCIe fabric.

US Patent:

20200242065, Jul 30, 2020

Filed:

Apr 20, 2020

Appl. No.:

16/852676

Inventors:

- Broomfield CO, US
German Kazakov - Longmont CO, US
Christopher R. Long - Colorado Springs CO, US
Jason Breakstone - Broomfield CO, US

Assignee:

Liqid Inc. - Broomfield CO

International Classification:

G06F 13/40
G06T 1/20
G06F 13/42
G06F 12/02
G06F 9/50
G06F 13/28

Abstract:

Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes receiving user input to establish a compute unit comprising a host processor and at least two graphics processing units (GPUs) having a peer-to-peer capability. The method also includes instructing a management element for a communication fabric to form the compute unit and communicatively couple the host processor and the at least two GPUs over the communication fabric. The method also includes instructing the management element to establish an isolation function to form the peer arrangement between the at least two GPUs in the communication fabric, where the isolation function isolates a first address domain associated with the at least two GPUs from at least a second address domain associated with the host processor by at least establishing synthetic devices representing the at least two GPUs in the second address domain.