Jason M Carroll

US Patent:

20130169635, Jul 4, 2013

Filed:

May 22, 2012

Appl. No.:

13/477808

Inventors:

Jason CARROLL - Oviedo FL, US
Vineet GOEL - Winter Park FL, US
Mangesh NIJASURE - Orlando FL, US
Todd E. MARTIN - Orlando FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06T 11/20
G06T 17/20

US Classification:

345423, 345441

Abstract:

Disclosed herein is a vertex core. The vertex core includes a reset scanner configured to remove reset indices and partial primitives in an input stream and resolve draw calls into sub-draw calls at reset index boundaries; and provide the resolved sub-draw calls to a plurality of downstream vertex grouper tessellators.

US Patent:

20140078156, Mar 20, 2014

Filed:

Sep 14, 2012

Appl. No.:

13/616474

Inventors:

Jason Carroll - Oviedo FL, US
Vineet Goel - Winter Park FL, US
Mangesh Nijasure - Orlando FL, US
Todd E. Martin - Orlando FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06T 1/20

US Classification:

345505

Abstract:

A system, method and a computer program product are provided for distributing prim groups for parallel processing in a single clock cycle. A work distributor divides a draw call for primitive processing into a plurality of prim groups according to a prim group size. The work distributor then distributes the plurality of prim groups to a plurality of shader engines for parallel processing of the plurality of prim groups during a clock cycle. The size of a prim group and a number of prim groups are scaled to the plurality of shader engines.

US Patent:

20200301753, Sep 24, 2020

Filed:

Mar 22, 2019

Appl. No.:

16/361910

Inventors:

- Cupertino CA, US
Jason D. Carroll - Oviedo FL, US
Karl D. Mann - Geneva FL, US

International Classification:

G06F 9/52

Abstract:

Techniques are disclosed relating to processing a control stream such as a compute control stream. In some embodiments, the control stream includes kernels and commands for multiple substreams. In some embodiments, multiple substream processors are each configured to: fetch and parse portions of the control stream corresponding to an assigned substream and, in response to a neighbor barrier command in the assigned substream that identifies another substream, communicate the identified other substream to a barrier clearing circuitry. In some embodiments, the barrier clearing circuitry is configured to determine whether to allow the assigned substream to proceed past the neighbor barrier command based on communication of a most-recently-completed command from a substream processor to which the other substream is assigned (e.g., based on whether the most-recently-completed command meets a command identifier communicated in the neighbor barrier command). The disclosed techniques may facilitate parallel control stream parsing and substream synchronization.