Jason R Carroll

US Patent:

20110057931, Mar 10, 2011

Filed:

Feb 18, 2010

Appl. No.:

12/708331

Inventors:

Vineet GOEL - Winter Park FL, US
Jason David CARROLL - Oviedo FL, US
Brian BUCHNER - Oviedo FL, US
Mangesh NIJASURE - Orlando FL, US

International Classification:

G06T 17/20

US Classification:

345423

Abstract:

Disclosed herein methods, apparatuses, and systems for performing graphics processing. In this regard, a processing unit includes a tessellation module and a connectivity module. The tessellation module is configured to sequentially tessellate portions of a geometric shape to provide a series of tessellation points for the geometric shape. The connectivity module is configured to connect one or more groups of the tessellation points into one or more primitives in an order in which the series of tessellation points is provided.

US Patent:

20130162651, Jun 27, 2013

Filed:

Dec 23, 2011

Appl. No.:

13/336635

Inventors:

Todd Martin - Orlando FL, US
Mangesh Nijasure - Orlando FL, US
Vineet Goel - Winter Park FL, US
Jason David Carroll - Oviedo FL, US

International Classification:

G06T 11/20

US Classification:

345441

Abstract:

Methods, systems, and computer readable media embodiments are disclosed for generating primitives in a grid. Embodiments include generating a set of vertices in a section of the grid, selecting one or more vertices in the set of vertices in an order based on a proximity of the vertices to a boundary edge of the grid, and generating primitives based on the order of the selected vertices.

US Patent:

20130169634, Jul 4, 2013

Filed:

Apr 18, 2012

Appl. No.:

13/449410

Inventors:

Vineet GOEL - Winter Park FL, US
Jason David Carroll - Oviedo FL, US
Mangesh Nijasure - Orlando FL, US
Todd Martin - Orlando FL, US

International Classification:

G06T 17/20

US Classification:

345423

Abstract:

Embodiments include an apparatus, a computer readable medium and a method for distributing tessellations within an accelerated processing device (APD) including at least two compute units. Embodiments include processing a plurality of patches in a first compute unit using a hull shader to generate hull shader output data. Once generated, hull shader output data is stored to an off-chip memory when tessellation factors associated with the shader program are greater than a configured threshold. Once stored in the off-chip memory, at least a portion of the hull shader output data is dynamically processed using a second compute unit.

US Patent:

20130169635, Jul 4, 2013

Filed:

May 22, 2012

Appl. No.:

13/477808

Inventors:

Jason CARROLL - Oviedo FL, US
Vineet GOEL - Winter Park FL, US
Mangesh NIJASURE - Orlando FL, US
Todd E. MARTIN - Orlando FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06T 11/20
G06T 17/20

US Classification:

345423, 345441

Abstract:

Disclosed herein is a vertex core. The vertex core includes a reset scanner configured to remove reset indices and partial primitives in an input stream and resolve draw calls into sub-draw calls at reset index boundaries; and provide the resolved sub-draw calls to a plurality of downstream vertex grouper tessellators.

US Patent:

20140078156, Mar 20, 2014

Filed:

Sep 14, 2012

Appl. No.:

13/616474

Inventors:

Jason Carroll - Oviedo FL, US
Vineet Goel - Winter Park FL, US
Mangesh Nijasure - Orlando FL, US
Todd E. Martin - Orlando FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06T 1/20

US Classification:

345505

Abstract:

A system, method and a computer program product are provided for distributing prim groups for parallel processing in a single clock cycle. A work distributor divides a draw call for primitive processing into a plurality of prim groups according to a prim group size. The work distributor then distributes the plurality of prim groups to a plurality of shader engines for parallel processing of the plurality of prim groups during a clock cycle. The size of a prim group and a number of prim groups are scaled to the plurality of shader engines.

US Patent:

20200301753, Sep 24, 2020

Filed:

Mar 22, 2019

Appl. No.:

16/361910

Inventors:

- Cupertino CA, US
Jason D. Carroll - Oviedo FL, US
Karl D. Mann - Geneva FL, US

International Classification:

G06F 9/52

Abstract:

Techniques are disclosed relating to processing a control stream such as a compute control stream. In some embodiments, the control stream includes kernels and commands for multiple substreams. In some embodiments, multiple substream processors are each configured to: fetch and parse portions of the control stream corresponding to an assigned substream and, in response to a neighbor barrier command in the assigned substream that identifies another substream, communicate the identified other substream to a barrier clearing circuitry. In some embodiments, the barrier clearing circuitry is configured to determine whether to allow the assigned substream to proceed past the neighbor barrier command based on communication of a most-recently-completed command from a substream processor to which the other substream is assigned (e.g., based on whether the most-recently-completed command meets a command identifier communicated in the neighbor barrier command). The disclosed techniques may facilitate parallel control stream parsing and substream synchronization.

US Patent:

20140152675, Jun 5, 2014

Filed:

Dec 5, 2012

Appl. No.:

13/705479

Inventors:

- Sunnyvale CA, US
Mangesh Nijasure - Orlando FL, US
Jason Carroll - Oviedo FL, US
Randy W. Ramsey - Oviedo FL, US
Brian A. Buchner - Oviedo FL, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06T 15/00

US Classification:

345506

Abstract:

A system, method and a computer-readable medium for load balancing patch processing pre-tessellation are provided. The patches for drawing objects on a display screen are distributed to shader engines for parallel processing. Each shader engine generates tessellation factors for a patch, wherein a value of generated tessellation factors for the patch is unknown prior to distribution. The patches are redistributed to the shader engines pre-tessellation to load balance the shader engines for processing the patches based on the value of tessellation factors in each patch.