Jason Chen

US Patent:

8107386, Jan 31, 2012

Filed:

Feb 7, 2008

Appl. No.:

12/027725

Inventors:

Rakesh Kumar - Austin TX, US
Jay Shah - Austin TX, US
Jason Xiaoguang Chen - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04J 1/16

US Classification:

370252

Abstract:

In one example embodiment, a system and method is provided that includes establishing a plurality of Pseudo Wire (PW) connections between a first network appliance region and a second network appliance region to transmit data from the first network appliance region to the second network appliance region along an active PW. Further, the method includes disabling the active PW when a failure of the active PW is detected. Additionally, the method may include selecting an inactive PW to become a new active PW such that the data may be transmitted from the first network appliance region to the second network appliance region. Moreover, the method includes switching from the active PW to the new active PW.

US Patent:

8370684, Feb 5, 2013

Filed:

Nov 11, 2010

Appl. No.:

12/944269

Inventors:

G. Glenn Henry - Austin TX, US
Darius D. Gaskins - Austin TX, US
Jason Chen - Austin TX, US

Assignee:

VIA Technologies, Inc. - New Taipei

International Classification:

G06F 11/26

US Classification:

714 23, 714 30

Abstract:

A microprocessor includes a bus interface unit that interfaces the microprocessor to a bus that includes a signal that, when asserted, instructs all bus agents to refrain from initiating bus transactions. Microcode causes the bus interface unit to assert the signal in response to detecting an event and resets the microprocessor, but does not reset a portion of the bus interface unit that asserts the signal on the bus. After the reset, the microcode causes the bus interface unit to deassert the signal on the bus. Additionally, the microcode sets a flag and saves the microprocessor state to memory before resetting itself, but does not reset the interrupt controller. After the reset, the microcode reloads the state of the microprocessor from the memory. However, if the microcode determines that the flag is set, it forgoes reloading the state of the interrupt controller.

US Patent:

8639919, Jan 28, 2014

Filed:

Nov 10, 2011

Appl. No.:

13/293268

Inventors:

G. Glenn Henry - Austin TX, US
Jason Chen - Austin TX, US

Assignee:

VIA Technologies, Inc. - New Taipei

International Classification:

G06F 9/00
G06F 9/24
G06F 9/44
G06F 15/177

US Classification:

713 2, 713 1, 712227, 717124

Abstract:

A microprocessor is provided with a reset logic flag and corresponding reset microcode that selectively enables the reset microcode to set up and enable debug logic before the microprocessor subsequently fetches and executes user instructions. When the reset logic flag is set to a debug mode, the reset microcode configures and enables the microprocessor's debug logic before the microprocessor subsequently fetches and executes user instructions. When the reset logic flag is set to a normal mode, the reset microcode refrains from configuring and enabling the microprocessor's debug logic. The reset logic flag is indicated by an alterable fuse or a debugger-programmable scan register. Debug configuration initialization values are also provided by several alternative structures, including the reset microcode itself, alterable fuses, and debugger-programmable scan registers. Corresponding methods are also provided for configuring the debug logic of a microprocessor.

US Patent:

20110185160, Jul 28, 2011

Filed:

Dec 10, 2010

Appl. No.:

12/964949

Inventors:

Darius D. Gaskins - Austin TX, US
Jason Chen - Austin TX, US
Rodney E. Hooker - Austin TX, US

Assignee:

VIA TECHNOLOGIES, INC. - Taipei

International Classification:

G06F 9/30
G06F 1/14
G06F 13/28

US Classification:

712216, 713502, 710308, 712E09023

Abstract:

A method for debugging a multi-core microprocessor includes causing the microprocessor to perform an actual execution of instructions and obtaining from the microprocessor heartbeat information that specifies an actual execution sequence of the instructions by the plurality of cores relative to one another, commanding a corresponding plurality of instances of a software functional model of the cores to execute the instructions according to the actual execution sequence specified by the heartbeat information to generate simulated results of the execution of the instructions, and comparing the simulated results with actual results of the execution of the instructions to determine whether they match. Each core outputs an instruction execution indicator indicating the number of instructions executed by the core each core clock. A heartbeat generator generates a heartbeat indicator for each core on an external bus that indicates the number of instructions executed by each core during each external bus clock cycle.

US Patent:

20160293273, Oct 6, 2016

Filed:

Nov 26, 2014

Appl. No.:

14/890421

Inventors:

- Shanghai, CN
STEPHAN GASKINS - Austin TX, US
DOUGLAS R. REED - Austin TX, US
JASON CHEN - Austin TX, US

International Classification:

G11C 29/38
G11C 29/44

Abstract:

A processor includes a cache memory having a plurality of entries. Each of the entries holds data of a cache line, a state of the cache line and a tag of the cache line. The cache memory includes an engine comprising one or more finite state machines. The processor also includes an interface to a bus over which the processor writes back modified cache lines from the cache memory to the system memory in response to encountering an architectural writeback and invalidate instruction. The processor also invalidates the state of the entries of the cache memory in response to encountering the architectural writeback and invalidate instruction. In response to being instructed to perform a cache diagnostic operation, for each entry of the entries, the engine writes the state and the tag of the entry on the bus and does not invalidate the state of the entry.

US Patent:

20160197811, Jul 7, 2016

Filed:

Nov 3, 2015

Appl. No.:

14/931602

Inventors:

- San Jose CA, US
Hsiang Ann Chen - Austin TX, US
Jason Xiaoguang Chen - San Jose CA, US
Rakesh Kumar - Austin TX, US

International Classification:

H04L 12/26
H04L 12/723

Abstract:

A method and apparatus to provide hop-by-hop tracking for a communication network is described. In one embodiment, each router verifies that a next downstream router supports tracking and in response, adds a tracking indicator and a timestamp to the data packet. An end router provides a compilation of all the timestamps back to the originating router.

US Patent:

20140133342, May 15, 2014

Filed:

Jan 21, 2014

Appl. No.:

14/160089

Inventors:

- San Jose CA, US
Hsiang Ann Chen - Austin TX, US
Jason Xiaoguang Chen - San Jose CA, US
Rakesh Kumar - Austin TX, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

H04L 12/26
H04L 12/24

US Classification:

370252

Abstract:

A method and apparatus to provide hop-by-hop tracking for a communication network is described. In one embodiment, a router verifies that a next downstream router does not support tracking and in response terminates hop-by-hop tracking. An end router provides a compilation of all the timestamps back to the originating router.