Jason M Cox

US Patent:

7537158, May 26, 2009

Filed:

Jun 24, 2008

Appl. No.:

12/145295

Inventors:

Jason A. Cox - Raleigh NC, US
Pamela A. Nesbitt - Tampa FL, US
Lydia M. Do - Research Triangle Park NC, US
Lisa A. Seacat - San Francisco CA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 19/00

US Classification:

235385, 235383, 23546201, 705 26

Abstract:

A method for identifying product compatibility comprises retrieving product information for a plurality of products, the plurality of products, storing the product information for the plurality of products on at least one of a first storage device and a second storage device, identifying a first product and a second product as members of a collection of compatible products, aggregating the design codes of each of the members of the collection of compatible products, creating a collection code for the collection of compatible products, assigning the collection code to all members of the collection of compatible products, comparing the first product to the second product, determining whether the first product and the second product are members of the collection of compatible products, and providing a result of the determining whether the first product and the second product are members of the collection of compatible products.

US Patent:

7640414, Dec 29, 2009

Filed:

Nov 16, 2006

Appl. No.:

11/560443

Inventors:

Jason Alan Cox - Raleigh NC, US
Kevin Chih Kang Lin - Raleigh NC, US
Eric Francis Robinson - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711168, 711123, 711126, 711154, 711169, 712208, 712225

Abstract:

Methods, systems, and computer program products for forwarding store data to loads in a pipelined processor are provided. In one implementation, a processor is provided that includes a decoder operable to decode an instruction, and a plurality of execution units operable to respectively execute a decoded instruction from the decoder. The plurality of execution units include a load/store execution unit operable to execute decoded load instructions and decoded store instructions and generate corresponding load memory operations and store memory operations. The store queue is operable to buffer one or more store memory operations prior to the one or more memory operations being completed, and the store queue is operable to forward store data of the one or more store memory operations buffered in the store queue to a load memory operation on a byte-by-byte basis.

US Patent:

7689870, Mar 30, 2010

Filed:

Nov 17, 2006

Appl. No.:

11/561010

Inventors:

Jason A. Cox - Raleigh NC, US
Keith A. DeWeese - Cary NC, US
Robert J. Dorsey - Durham NC, US
Eric F. Robinson - Raleigh NC, US
Thuong Q. Truong - Austin TX, US
Mark J. Wolski - Apex NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 45, 714 39

Abstract:

A method and system for creating trace triggers from non-concurrent events, the system comprising: a trace trigger mechanism including: a plurality of multiplexers for breaking down a plurality of signals into a plurality of groups of signals; a pattern match mechanism for matching the plurality of signals to form a plurality of events, and a trace array trigger control block to perform one or more functions on the plurality of independently controlled events in order to create flexible trace trigger controls from non-concurrent events to control the starting and stopping of a data gathering function such as is used to capture trace data.

US Patent:

7752393, Jul 6, 2010

Filed:

May 4, 2008

Appl. No.:

12/114785

Inventors:

Jason A. Cox - Raleigh NC, US
Kevin C. K. Lin - Raleigh NC, US
Eric F. Robinson - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711126, 711123, 711154, 711168, 711169, 712208, 712225

Abstract:

A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding store data to loads in a pipelined processor is provided. In one implementation, a processor is provided that includes a decoder operable to decode an instruction, and a plurality of execution units operable to respectively execute a decoded instruction from the decoder. The plurality of execution units include a load/store execution unit operable to execute decoded load instructions and decoded store instructions and generate corresponding load memory operations and store memory operations. The store queue is operable to buffer one or more store memory operations prior to the one or more memory operations being completed, and the store queue is operable to forward store data of the one or more store memory operations buffered in the store queue to a load memory operation on a byte-by-byte basis.

US Patent:

7836257, Nov 16, 2010

Filed:

Dec 19, 2007

Appl. No.:

11/959804

Inventors:

Robert John Dorsey - Durham NC, US
Jason Alan Cox - Raleigh NC, US
Hien Minh Le - Cedar Park TX, US
Richard Nicholas - Round Rock TX, US
Eric Francis Robinson - Raleigh NC, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corpation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711133, 711118, 711119, 711124, 711134, 711136, 711141, 711159, 711160

Abstract:

A method for managing a cache operates in a data processing system with a system memory and a plurality of processing units (PUs). A first PU determines that one of a plurality of cache lines in a first cache of the first PU must be replaced with a first data block, and determines whether the first data block is a victim cache line from another one of the plurality of PUs. In the event the first data block is not a victim cache line from another one of the plurality of PUs, the first cache does not contain a cache line in coherency state invalid, and the first cache contains a cache line in coherency state moved, the first PU selects a cache line in coherency state moved, stores the first data block in the selected cache line and updates the coherency state of the first data block.

US Patent:

8184092, May 22, 2012

Filed:

May 22, 2008

Appl. No.:

12/125428

Inventors:

Jason Alan Cox - Raleigh NC, US
Lydia Mai Do - Research Triangle Park NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G09G 5/00

US Classification:

345156, 345165, 345179, 345175, 345173, 345174, 345176, 345177, 345178, 715863, 715864, 715865, 715866, 382103, 463 37

Abstract:

A method and system of utilizing a game console with motion sensing technology is provided. The present invention, in various implementations, provides for a method for generating one or more symbols in response to one or more gestures using an input device of a gaming system. The method comprises providing the input device being capable of generating one or more gesture signals in response to one or more gestures and being operable to select a mode of one or more operational states. The method also provides for generating one or more gesture signals corresponding to the one or more gestures, respectively; mapping the one or more generated gesture signals in relation to one or more symbols, respectively; and, transmitting the one or more symbols corresponding to the respective one or more gesture signals to an output.

US Patent:

8276193, Sep 25, 2012

Filed:

Oct 2, 2008

Appl. No.:

12/244063

Inventors:

Jason A. Cox - Raleigh NC, US
Lydia M. Do - Research Triangle Park NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 29/06

US Classification:

726 4, 463 25, 726 27, 709225, 709226, 715726, 715741, 715743

Abstract:

An Activity Access Control (AAC) utility controls access to applications and devices by allowing an administrator to set terms of use/access regarding a applications and/or devices for a group of users, whose activity are monitored. The AAC utility also enables administrator and user access to a compromise facility via a centralized access point to establish or request changes to the terms of use/access. The AAC utility allows the administrator to dynamically update information and set terms based on real-time information collected during activity monitoring. Dynamic updates may also occur based on the monitored user's request, the priority of the requesting user(s), historical data, occurrence of a special event, completion of other internal or/external tasks, and/or pre-set limitations or thresholds. In addition, the AAC utility facilitates the real-time display or publishing of the terms of use, status information, and statistical information to users and the administrator.

US Patent:

8296520, Oct 23, 2012

Filed:

Dec 19, 2007

Appl. No.:

11/959652

Inventors:

Hien Minh Le - Cedar Park TX, US
Jason Alan Cox - Raleigh NC, US
Robert John Dorsey - Durham NC, US
Richard Nicholas - Round Rock TX, US
Eric Francis Robinson - Raleigh NC, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/08

US Classification:

711124, 711121, 711135, 711143

Abstract:

A method for managing data operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least another one of the plurality of PUs. A first PU selects a castout cache line of a plurality of cache lines in a first cache of the first PU to be castout of the first cache. The first PU sends a request to a second PU, wherein the second PU is a neighboring PU of the first PU, and the request comprises a first address and first coherency state of the selected castout cache line. The second PU determines whether the first address matches an address of any cache line in the second PU. The second PU sends a response to the first PU based on a coherency state of each of a plurality of cache lines in the second cache and whether there is an address hit. The first PU determines whether to transmit the castout cache line to the second PU based on the response.