Jason M Garcia

US Patent:

7183493, Feb 27, 2007

Filed:

Jun 30, 2004

Appl. No.:

10/883433

Inventors:

Jason A. Garcia - Chandler AZ, US
John J. Beatty - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K 1/09

US Classification:

174257, 174256

Abstract:

According to one aspect of the invention, an electronic assembly is provided. The electronic assembly includes a first substrate having an integrated circuit formed therein and a second substrate. The first and second substrates are interconnected by a plurality of bi-material interconnects that are electrically connected to the integrated circuit and have a first component comprising a conductive first material with a first coefficient of thermal expansion and a second component comprising a second material with a second coefficient of thermal expansion. The first and second components are connected and shaped such that when the temperature of the bi-material interconnects changes the interconnects each bend towards the first or second component. When the temperature of the second substrate increases, the second substrate expands away from a central portion thereof. The bi-material interconnects are arranged such that the bi-material interconnects bend away from the central portion of the second substrate.

US Patent:

7276396, Oct 2, 2007

Filed:

Oct 6, 2004

Appl. No.:

10/959931

Inventors:

Jason A. Garcia - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/00

US Classification:

438106, 438108, 438110, 438113, 257778, 257782, 156510

Abstract:

A system may include singulation of a semiconductor wafer to separate a plurality of integrated circuit die that are integrated into the semiconductor wafer; coupling of a support to an integrated circuit substrate of one of the plurality of integrated circuit die, and decoupling of the one integrated circuit die from the singulated semiconductor wafer while the support is coupled to the integrated circuit substrate. According to some embodiments, a second side of the one integrated circuit die is not touched during the coupling and the decoupling, the second side being opposite to the integrated circuit substrate.

US Patent:

7352039, Apr 1, 2008

Filed:

Mar 24, 2005

Appl. No.:

11/089906

Inventors:

Jason A. Garcia - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/10

US Classification:

257415, 257E23194

Abstract:

Various methods and apparatuses are described in which a micro-electro-mechanical systems (MEMS) device is encapsulated with a material having a variable viscosity with a viscosity value high enough to retard foreign material from contacting the MEMS device during an electronic package assembly process. The material having the variable viscosity may be affixed to a cavity area surrounding the MEMS device prior to an epoxy being dispensed onto the electronic package assembly. The temperature and pressure conditions of the electronic package assembly process may be controlled to ensure when the epoxy is dispensed that the material having the variable viscosity has a high enough viscosity value to retard foreign material from contacting the MEMS device during the electronic package assembly process.

US Patent:

7421778, Sep 9, 2008

Filed:

Mar 22, 2006

Appl. No.:

11/388100

Inventors:

Jason A. Garcia - Chandler AZ, US
John J. Beatty - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K 3/36

US Classification:

29830, 29842, 29843, 29874, 29884

Abstract:

According to one aspect of the invention, an electronic assembly is provided. The electronic assembly includes a first substrate having an integrated circuit formed therein and a second substrate. The first and second substrates are interconnected by a plurality of bi-material interconnects that are electrically connected to the integrated circuit and have a first component comprising a conductive first material with a first coefficient of thermal expansion and a second component comprising a second material with a second coefficient of thermal expansion. The first and second components are connected and shaped such that when the temperature of the bi-material interconnects changes the interconnects each bend towards the first or second component. When the temperature of the second substrate increases, the second substrate expands away from a central portion thereof. The bi-material interconnects are arranged such that the bi-material interconnects bend away from the central portion of the second substrate.

US Patent:

8064728, Nov 22, 2011

Filed:

Mar 30, 2007

Appl. No.:

11/694893

Inventors:

Jason A. Garcia - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06K 9/00
G06K 9/46
G06K 9/36
G06K 9/62
G06K 9/66
G06K 7/10
H04N 9/47
H04N 7/18

US Classification:

382287, 382103, 382128, 382145, 382153, 382190, 382224, 382276, 348 87, 348135, 23546201

Abstract:

The formation of marks on devices is described. In one embodiment, a method for marking a device includes forming a plurality of unique marks sequentially on a device. The method includes defining a virtual array having a plurality of cells extending in an x-direction and a plurality of cells extending in a y-direction, wherein the marks are each positioned in a cell in the virtual array. The method also includes capturing an image including the relative cell position of the marks within the virtual array and converting the relative position of the marks within the virtual array into a set of coordinates including an x value along the x-direction and a y value along the y-direction for each of the marks. The method also includes generating a device identification using a plurality of the x values and the y values. Other embodiments are described and claimed.

US Patent:

7262509, Aug 28, 2007

Filed:

May 11, 2004

Appl. No.:

10/843885

Inventors:

Jason A. Garcia - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/28
H01L 23/29

US Classification:

257778, 257691, 257737, 257773, 257776, 257788, 257E23021, 257E23069

Abstract:

A microelectronic assembly is provided having a MEMS substrate, a MEMS device on the MEMS substrate, the MEMS device having a MEMS component which is movable relative to the MEMS substrate, a cover piece having a side over a side of the MEMS substrate on which the MEMS device is located, and a plurality of perimeter components, each having opposing portions sealing with the MEMS substrate and the cover piece respectively, the perimeter components forming a perimeter around the MEMS device.

US Patent:

20030067750, Apr 10, 2003

Filed:

Oct 4, 2001

Appl. No.:

09/971948

Inventors:

Jason Garcia - Chandler AZ, US

International Classification:

H05K007/20

US Classification:

361/702000

Abstract:

A wirebonded microelectronic package including a microelectronic die attached by a back surface to a mounting surface of a recess formed in a substrate and a heat dissipation device thermally contacting said microelectronic die active surface. A plurality of bond wires electrically connects bond pads on the microelectronic die active surface to a plurality of corresponding traces within the recess.

US Patent:

20060019468, Jan 26, 2006

Filed:

Jul 21, 2004

Appl. No.:

10/897067

Inventors:

John Beatty - Chandler AZ, US
Jason Garcia - Chandler AZ, US

International Classification:

H01L 21/78
H01L 21/48
H01L 21/50

US Classification:

438464000, 438460000, 438113000, 438114000

Abstract:

A method of manufacturing a plurality of electronic devices is provided. Each one of a plurality of first conductive terminals on a plurality of integrated circuits formed on a device wafer is connected to a respective one of a plurality of second conductive terminals on a carrier wafer, thereby forming a combination wafer assembly. The combination wafer assembly is singulated between the integrated circuits to form separate electronic assemblies. Each electronic assembly has a respective die from a separated portion of the device wafer and a carrier substrate from a separated portion of the carrier wafer. The process of fabricating electronic assemblies is simplified and costs are reduced because the dies are connected to the carrier substrate at wafer level, i.e. before singulation. The combination wafer assembly also allows for an underfill material to be introduced and to cured at wafer level and for thinning of the device wafer at wafer level without requiring a separate supporting substrate. Alignment between the device wafer and the carrier wafer can be tested by conducting a current through first and second conductors in the device and carrier wafers, respectively.