Jason Ronald Howard

US Patent:

20200401412, Dec 24, 2020

Filed:

Jun 24, 2019

Appl. No.:

16/450300

Inventors:

- Santa Clara CA, US
Joshua B. FRYMAN - Corvallis OR, US
Vincent CAVE - Hillsboro OR, US
Eric M. SCHWARTZ - Portland OR, US
Ivan B. GANEV - Portland OR, US
Jason M. HOWARD - Portland OR, US
Ankit MORE - San Mateo CA, US
Shaden SMITH - Mountain View CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/38
G06F 9/52

Abstract:

Disclosed embodiments relate to hardware support for dual-memory atomic operations. In one example, a processor includes multiple cores, each including multiple multi-threaded pipelines (MTPs), each associated with a memory, an atomic unit (ATMU) to perform atomic operations and a write-combine buffer (WCB) to manage access to and locks of cache lines in the associated memory, each MTP including fetch and decode stages to fetch and decode an instruction having fields to specify first and second memory locations and an opcode calling for a first MTP to send a request to a second MTP of the multiple MTPs, the second MTP being associated with a memory to which the first memory location is mapped, and to perform an atomic dual-memory operation on the first and second memory locations using its associated ATMU and WCB to perform the request.

US Patent:

20200004587, Jan 2, 2020

Filed:

Jun 29, 2018

Appl. No.:

16/024343

Inventors:

- Santa Clara CA, US
Joshua Fryman - Corvallis OR, US
Jason Howard - Portland OR, US
Sang Phill Park - Hillsboro OR, US
Robert Pawlowski - Portland OR, US
Michael Abbott - Hillsboro OR, US
Scott Cline - Beaverton OR, US
Samkit Jain - Hillsboro OR, US
Ankit More - San Francisco CA, US
Vincent Cave - Hillsboro OR, US
Fabrizio Petrini - Palo Alto CA, US
Ivan Ganev - Hillsboro OR, US

International Classification:

G06F 9/48
G06F 9/38
G06F 9/30

Abstract:

Embodiments of apparatuses, methods, and systems for a multithreaded processor core with hardware-assisted task scheduling are described. In an embodiment, a processor includes a first hardware thread, a second hardware thread, and a task manager. The task manager is to issue a task to the first hardware thread. The task manager includes a hardware task queue in which to store a plurality of task descriptors. Each of the task descriptors is to represent one of a single task, a collection of iterative tasks, and a linked list of tasks.