Jason E Howard

US Patent:

6988119, Jan 17, 2006

Filed:

Jun 29, 2001

Appl. No.:

09/895526

Inventors:

Yatin Hoskote - Portland OR, US
Jason M Howard - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 7/42

US Classification:

708505

Abstract:

The proposed fast single precision floating point accumulator of the present invention uses base 32 computation in an attempt to completely remove the need for a costly 8-bit subtractor in the exponent path as is commonly found in conventional designs. It also replaces the expensive variable shifter in the mantissa path with a constant shifter which significantly reduces the cost of the present invention relative to earlier floating point accumulators. The variable shifter required for base 2 to base 32 conversion has been moved outside the accumulator loop. This approach allows comparison of the two input exponents using a comparator. The mantissas are shifted by constant amount to bring them into partial alignment. They are then added or the appropriate mantissa is chosen as the result. The input stream to the accumulator does not need to be cumulative.

US Patent:

8574731, Nov 5, 2013

Filed:

Oct 29, 2008

Appl. No.:

12/260614

Inventors:

Robert M. Johnson - Lake Zurich IL, US
Jason N. Howard - Alpharetta GA, US

Assignee:

Motorola Mobility LLC - Libertyville IL

International Classification:

H01M 8/04

US Classification:

429 9, 429428, 320101

Abstract:

A method () and device () for augmenting the useful life of an energy storage device in a portable electronic device is disclosed. The method () can include the steps of: providing () a power module comprising a fuel cell and a battery; determining () relative humidity; and controlling () the operations of the power module in response to the determined relative humidity. Advantageously, the method () and device () can augment and prolong the useful life of an energy storage device in a portable electronic device, with minimal power drain.

US Patent:

20030154227, Aug 14, 2003

Filed:

Feb 8, 2002

Appl. No.:

10/071373

Inventors:

Jason Howard - Beaverton OR, US
Yatin Hoskote - Portland OR, US
Sriram Vangal - Hillsboro OR, US

Assignee:

Intel Corporation

International Classification:

G06F007/38

US Classification:

708/495000

Abstract:

A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. The adder circuit includes intermediate registers to provide multi-threaded capability. Products interleaved in time are accumulated into separate sums simultaneously.

US Patent:

20080172359, Jul 17, 2008

Filed:

Jan 11, 2007

Appl. No.:

11/622287

Inventors:

Louis J. Lundell - Buffalo Grove IL, US
Jason N. Howard - Alpharetta GA, US
Thomas J. Weigert - Palatine IL, US

Assignee:

MOTOROLA, INC. - Schaumburg IL

International Classification:

G06F 7/06
G10L 15/26
G10L 15/00

US Classification:

707 3, 704251, 704235, 704E15043, 707E17014

Abstract:

A system [] includes a database [] to store a user profile for a user []. The user profile contains user-specific information. An intelligent agent [] monitors a conversation involving the user for at least one keyword. In response to detecting the at least one keyword, the intelligent agent: (a) searches the user profile for at least one item corresponding to the at least one keyword; (b) retrieves the at least one item from the user profile; and (c) determines a relevance between the at least one keyword and the at least one item. An application communication element [] communicates application information corresponding to the at least one item to an application program in response to the relevance exceeding a predetermined threshold.

US Patent:

62786040, Aug 21, 2001

Filed:

Dec 18, 1997

Appl. No.:

8/992483

Inventors:

Hitendra K. Patel - Palatine IL
Jason N. Howard - Lawrenceville GA
Richard H. Jung - Park Ridge IL

Assignee:

Motorola Inc - Schaumburg IL

International Classification:

H01G 9004
H01G 538

US Classification:

361502

Abstract:

A multiple cell capacitor (200) includes at least first and second capacitor cells (260) and a cell balancing circuit (265) electrically coupled to the first and second capacitor cells (260). Packaging material (280) encloses the first and second capacitor cells (260) and the cell balancing circuit (265). The cell balancing circuit (265) can include, for each capacitor cell (260), a resistor (265) formed electrically in parallel with that capacitor cell (260).

US Patent:

57442584, Apr 28, 1998

Filed:

Dec 23, 1996

Appl. No.:

8/774048

Inventors:

Lijun Bai - Vernon Hills IL
Changming Li - Vernon Hills IL
Anaba A. Anani - Lawrenceville GA
George Thomas - Lawrenceville GA
Han Wu - Barrington IL
Ke Keryn Lian - Palatine IL
Frank R. Denton - Lawrenceville GA
Jason N. Howard - Lawrenceville GA

Assignee:

Motorola,Inc. - Schaumburg IL

International Classification:

H01M 436

US Classification:

429 3

Abstract:

A hybrid electrode for a high power, high energy, electrical storage device contains both a high-energy electrode material (42) and a high-rate electrode material (44). The two materials are deposited on a current collector (40), and the electrode is used to make an energy storage device that exhibits both the high-rate capability of a capacitor and the high energy capability of a battery. The two materials can be co-deposited on the current collector in a variety of ways, either in superimposed layers, adjacent layers, intermixed with each other or one material coating the other to form a mixture that is then deposited on the current collector.

US Patent:

20220413855, Dec 29, 2022

Filed:

Jun 25, 2021

Appl. No.:

17/359305

Inventors:

- Santa Clara CA, US
Jason Howard - Portland OR, US
Joshua Fryman - Corvallis OR, US

International Classification:

G06F 9/30
G06F 9/38
G06F 12/0875

Abstract:

Techniques for operating on an indirect memory access instruction, where the instruction accesses a memory location via at least one indirect address. A pipeline processes the instruction and a memory operation engine generates a first access to the at least one indirect address and a second access to a target address determined by the at least one indirect address. A cache memory used with the pipeline and the memory operation engine caches pointers. In response to a cache hit when executing the indirect memory access instruction, operations dereference a pointer to obtain the at least one indirect address, not set a cache bit, and return data for the instruction without storing the data in the cache memory; and in response to a cache miss, operations set the cache bit, obtain, and store a cache line for a missed pointer, and return data without storing the data in the cache memory.

US Patent:

20220414038, Dec 29, 2022

Filed:

Jun 25, 2021

Appl. No.:

17/358832

Inventors:

- Santa Clara CA, US
BHARADWAJ KRISHNAMURTHY - HILLSBORO OR, US
SHRUTI SHARMA - HILLSBORO OR, US
BYOUNGCHAN OH - Hillsboro OR, US
JING FANG - Santa Clara CA, US
DANIEL KLOWDEN - Portland OR, US
JASON HOWARD - Portland OR, US
JOSHUA FRYMAN - Corvallis OR, US

International Classification:

G06F 13/28

Abstract:

Systems, methods, and apparatuses for direct memory access instruction set architecture support for flexible dense compute using a reconfigurable spatial array are described. In one embodiment, a processor includes a first type of hardware processor core that includes a two-dimensional grid of compute circuits, a memory, and a direct memory access circuit coupled to the memory and the two-dimensional grid of compute circuits; and a second different type of hardware processor core that includes a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including a first field to identify a base address of two-dimensional data in the memory, a second field to identify a number of elements in each one-dimensional array of the two-dimensional data, a third field to identify a number of one-dimensional arrays of the two-dimensional data, a fourth field to identify an operation to be performed by the two-dimensional grid of compute circuits, and a fifth field to indicate the direct memory access circuit is to move the two-dimensional data indicated by the first field, the second field, and the third field into the two-dimensional grid of compute circuits and the two-dimensional grid of compute circuits is to perform the operation on the two-dimensional data according to the fourth field, and an execution circuit to execute the decoded single instruction according to the fields