Jason V Howard

Address:

1155 Cumberland Ave, Syracuse, NY 13210

VIN:

5TELU42N57Z357038

Make:

TOYOTA

Model:

TACOMA

Year:

2007

US Patent:

6988119, Jan 17, 2006

Filed:

Jun 29, 2001

Appl. No.:

09/895526

Inventors:

Yatin Hoskote - Portland OR, US
Jason M Howard - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 7/42

US Classification:

708505

Abstract:

The proposed fast single precision floating point accumulator of the present invention uses base 32 computation in an attempt to completely remove the need for a costly 8-bit subtractor in the exponent path as is commonly found in conventional designs. It also replaces the expensive variable shifter in the mantissa path with a constant shifter which significantly reduces the cost of the present invention relative to earlier floating point accumulators. The variable shifter required for base 2 to base 32 conversion has been moved outside the accumulator loop. This approach allows comparison of the two input exponents using a comparator. The mantissas are shifted by constant amount to bring them into partial alignment. They are then added or the appropriate mantissa is chosen as the result. The input stream to the accumulator does not need to be cumulative.

US Patent:

20030154227, Aug 14, 2003

Filed:

Feb 8, 2002

Appl. No.:

10/071373

Inventors:

Jason Howard - Beaverton OR, US
Yatin Hoskote - Portland OR, US
Sriram Vangal - Hillsboro OR, US

Assignee:

Intel Corporation

International Classification:

G06F007/38

US Classification:

708/495000

Abstract:

A multiply-accumulate circuit includes a compressor tree to generate a product with a binary exponent and a mantissa in carry-save format. The product is converted into a number having a three bit exponent and a fifty-seven bit mantissa in carry-save format for accumulation. An adder circuit accumulates the converted products in carry-save format. The adder operates on floating point number representations having exponents with a least significant bit weight of thirty-two, and exponent comparisons within the adder exponent path are limited in size. The adder circuit includes intermediate registers to provide multi-threaded capability. Products interleaved in time are accumulated into separate sums simultaneously.

US Patent:

20220413855, Dec 29, 2022

Filed:

Jun 25, 2021

Appl. No.:

17/359305

Inventors:

- Santa Clara CA, US
Jason Howard - Portland OR, US
Joshua Fryman - Corvallis OR, US

International Classification:

G06F 9/30
G06F 9/38
G06F 12/0875

Abstract:

Techniques for operating on an indirect memory access instruction, where the instruction accesses a memory location via at least one indirect address. A pipeline processes the instruction and a memory operation engine generates a first access to the at least one indirect address and a second access to a target address determined by the at least one indirect address. A cache memory used with the pipeline and the memory operation engine caches pointers. In response to a cache hit when executing the indirect memory access instruction, operations dereference a pointer to obtain the at least one indirect address, not set a cache bit, and return data for the instruction without storing the data in the cache memory; and in response to a cache miss, operations set the cache bit, obtain, and store a cache line for a missed pointer, and return data without storing the data in the cache memory.

US Patent:

20220414038, Dec 29, 2022

Filed:

Jun 25, 2021

Appl. No.:

17/358832

Inventors:

- Santa Clara CA, US
BHARADWAJ KRISHNAMURTHY - HILLSBORO OR, US
SHRUTI SHARMA - HILLSBORO OR, US
BYOUNGCHAN OH - Hillsboro OR, US
JING FANG - Santa Clara CA, US
DANIEL KLOWDEN - Portland OR, US
JASON HOWARD - Portland OR, US
JOSHUA FRYMAN - Corvallis OR, US

International Classification:

G06F 13/28

Abstract:

Systems, methods, and apparatuses for direct memory access instruction set architecture support for flexible dense compute using a reconfigurable spatial array are described. In one embodiment, a processor includes a first type of hardware processor core that includes a two-dimensional grid of compute circuits, a memory, and a direct memory access circuit coupled to the memory and the two-dimensional grid of compute circuits; and a second different type of hardware processor core that includes a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including a first field to identify a base address of two-dimensional data in the memory, a second field to identify a number of elements in each one-dimensional array of the two-dimensional data, a third field to identify a number of one-dimensional arrays of the two-dimensional data, a fourth field to identify an operation to be performed by the two-dimensional grid of compute circuits, and a fifth field to indicate the direct memory access circuit is to move the two-dimensional data indicated by the first field, the second field, and the third field into the two-dimensional grid of compute circuits and the two-dimensional grid of compute circuits is to perform the operation on the two-dimensional data according to the fourth field, and an execution circuit to execute the decoded single instruction according to the fields

US Patent:

20220229723, Jul 21, 2022

Filed:

Apr 1, 2022

Appl. No.:

17/711646

Inventors:

- Santa Clara CA, US
Byoungchan Oh - Portland OR, US
Jason Howard - Portland OR, US
Sai Dheeraj Polagani - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/10

Abstract:

Memory requests are protected by encoding memory requests to include error correction codes. A subset of bits in a memory request are compared to a pre-defined pattern to determine whether the subset of bits matches a pre-defined pattern, where a match indicates that a compression can be applied to the memory request. The error correction code is generated for the memory request and the memory request is encoded to remove the subset of bits, add the error correction code, and add at least one metadata bit to the memory request to generate a protected version of the memory request, where the at least one metadata bit identifies whether the compression was applied to the memory request.

US Patent:

20220229795, Jul 21, 2022

Filed:

Apr 1, 2022

Appl. No.:

17/711209

Inventors:

Scott N. Cline - Portland OR, US
Ivan B. Ganev - Portland OR, US
Robert S. Pawlowski - Beaverton OR, US
Jason Howard - Portland OR, US
Joshua B. Fryman - Corvallis OR, US

International Classification:

G06F 13/24
G06F 9/30

Abstract:

A graph processing core includes a plurality of processing pipelines and an interrupt controller unit. Each processing pipeline executes one or more threads and includes, for each thread, a register indicating a currently executing program counter vector and another register indicating an interrupt or exception handler vector. The interrupt controller unit may receive interrupt or exception notifications from the processing pipelines, determine a handler vector based on the notification and a set of registers of the interrupt controller unit, and transmit the handler vector to the processing pipeline that issued the interrupt or exception notification. Further, the issuing pipeline may receive the handler vector from the interrupt controller unit, write a value in the first register into the second register, write the handler vector into the first register, and invoke an interrupt or exception hander based on the value written into the first register.

US Patent:

20220222075, Jul 14, 2022

Filed:

Apr 2, 2022

Appl. No.:

17/712104

Inventors:

Robert S. Pawlowski - Beaverton OR, US
Scott N. Cline - Portland OR, US
Jason Howard - Portland OR, US
Joshua B. Fryman - Corvallis OR, US
Ivan B. Ganev - Portland OR, US

International Classification:

G06F 9/30
G06F 12/02
G06F 12/1081

Abstract:

In one embodiment, a processor includes decode circuitry and memory offload circuitry. The decode circuitry decodes an instruction to perform a direct memory access (DMA) operation, which includes an opcode and one or more fields. The opcode indicates a type of DMA operation to be performed. The one or more fields indicate a destination memory region and one or more data operands. The memory offload circuitry offloads the instruction from an execution pipeline and performs the DMA operation.

US Patent:

20210389984, Dec 16, 2021

Filed:

Aug 24, 2021

Appl. No.:

17/410818

Inventors:

- Santa Clara CA, US
Ankit MORE - San Mateo CA, US
Jason M. HOWARD - Portland OR, US
Joshua B. FRYMAN - Corvallis OR, US
Tina C. ZHONG - Portland OR, US
Shaden SMITH - Mountain View CA, US
Samkit JAIN - Hillsboro OR, US
Vincent CAVE - Hillsboro OR, US
Bharadwaj KRISHNAMURTHY - Hillsboro OR, US

International Classification:

G06F 9/48
G06F 12/0815
G06F 9/35
G06F 9/38
G06F 13/28
G06F 9/30

Abstract:

Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.