Jason J Hudson

US Patent:

7327011, Feb 5, 2008

Filed:

Nov 2, 2005

Appl. No.:

11/266133

Inventors:

Jason D. Hudson - Eaton CO, US
Sean Erickson - Fort Collins CO, US
Michael J. Saunders - Fort Collins CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 29/00

US Classification:

257534, 257E27048, 257E21019, 438396

Abstract:

A plate to plate capacitor has a first plate, a second plate, and an insulating medium separating the first plate from the second plate. The first plate and the second plate are adapted and arranged to form an interlaced structure in which multiple capacitance surface areas in different planes, such as horizontal and vertical, are provided between said first and second plates. The plate to plate capacitor can be formed as a stack of layers in which one or more alternating first and third insulating layers each have first and second conductive lines configured therein and in which one or more second insulating layers having conductive vias formed therein interpose respective first and third insulating layers. The first and second conductive lines in the first insulating layer(s) are interconnected by the conductive vias to the first and second conductive lines, respectively, in the third layer(s) so as to interlace the first and second metal conductive lines together.

US Patent:

7397105, Jul 8, 2008

Filed:

Oct 12, 2005

Appl. No.:

11/248509

Inventors:

Sean Christopher Erickson - Fort Collins CO, US
Jason Dee Hudson - Eaton CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 21/425

US Classification:

257516, 257510, 257521, 257E21546

Abstract:

A deep n-well is formed beneath the area of a capacitor structure. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively and/or capacitively coupled surface currents to small areas that are then isolated from the rest of the chip.

US Patent:

7535330, May 19, 2009

Filed:

Sep 22, 2006

Appl. No.:

11/534340

Inventors:

Sean Christopher Erickson - Fort Collins CO, US
Jason Dee Hudson - Eaton CO, US
Michael J. Saunders - Fort Collins CO, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01F 5/00

US Classification:

336200

Abstract:

Multiple inductor structures and methods for providing low mutual inductance between the inductors are described. In various embodiments of the invention, the polarities of the inductors are positioned such that parasitic mutual inductance is reduced by causing electro-magnetic fields to at least partially cancel resulting in a reduction in interference between the inductors. The polarities of the magnetic fields produced by each inductor are opposite to each other so that at least a partial cancellation results when the fields interfere with each other.

US Patent:

7612427, Nov 3, 2009

Filed:

Sep 17, 2007

Appl. No.:

11/856196

Inventors:

Sean Christopher Erickson - Fort Collins CO, US
Jason Dee Hudson - Eaton CO, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 21/04

US Classification:

257510, 257516, 257647, 438424, 438425, 438427

Abstract:

A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively coupled surface currents to small areas that are then isolated from the rest of the chip.

US Patent:

20060128112, Jun 15, 2006

Filed:

Dec 12, 2004

Appl. No.:

11/010970

Inventors:

Sean Erickson - Fort Collins CO, US
Jason Hudson - Eaton CO, US

International Classification:

H01L 21/76

US Classification:

438424000

Abstract:

A deep n-well is formed beneath the area of an inductor coil. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively coupled surface currents to small areas that are then isolated from the rest of the chip.