Jason S Jacobs

US Patent:

6373310, Apr 16, 2002

Filed:

Oct 27, 2000

Appl. No.:

09/703988

Inventors:

Jason P. Jacobs - San Francisco CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 312

US Classification:

327217, 327219, 327215, 327225, 327218

Abstract:

A multiple input set/reset circuit is described that includes cross-coupled inverters connected between set and reset nodes. The set/reset circuit also includes at least one set input circuit coupled to the set node configured to receive a set signal and to drive the set node to a first logic state in response to the set signal asserted, and at least one reset input circuit coupled to the reset node configured to receive a reset signal and drive the reset node to the first logic state in response to the reset signal asserted. Incorporated into the set/reset circuit are a first switching circuit to change the logic state of one of the nodes to a second logic state when the other node changes the logic state to the first logic state, and a second switching circuit to disable the first switching circuit after the first and second nodes have completed a logical state change in response to a set or reset signal asserted.