Jason J Kim

US Patent:

6496361, Dec 17, 2002

Filed:

Nov 16, 1998

Appl. No.:

09/192837

Inventors:

Jason S. Kim - Campbell CA
Richard T. Hsu - San Jose CA

Assignee:

Acer Incorporated

International Classification:

G06F 116

US Classification:

361683, 361686, 395893, 348376

Abstract:

A laptop computer includes a video camera mounted to the lid, preferably embedded into the bezel above the display. The camera includes a CMOS imaging array, video data from which is communicated along a dedicated path from the camera to a graphics controller for output to the display, thereby bypassing the system bus. This makes it possible to display full frame, full data rate video with minimum impact on the overall system performance. Panning and zooming are implemented by software that controls the addresses in the pixel array from which data are transferred to the graphics controllers associated display memory.

US Patent:

6829628, Dec 7, 2004

Filed:

May 2, 2001

Appl. No.:

09/847982

Inventors:

Jason Seung-Min Kim - San Jose CA

Assignee:

PortalPlayer, Inc. - Santa Clara CA

International Classification:

G06F 102

US Classification:

708254

Abstract:

A random number generation system and method use the randomness in hardware circuitry start-up to generate a random seed for a random number. In a preferred embodiment, the instability of a phase locked loop is used.

US Patent:

6922771, Jul 26, 2005

Filed:

Apr 24, 2002

Appl. No.:

10/131359

Inventors:

Jason Seung-Min Kim - San Jose CA, US
Robert Quan - San Francisco CA, US

Assignee:

PortalPlayer, Inc. - Santa Clara CA

International Classification:

G06F015/76
G06F009/302
G06F007/38
G06F013/40

US Classification:

712 5, 712222, 711219, 710317, 708495

Abstract:

The present invention provides a vector floating point unit (FPU) comprising a product-terms bus, a summation bus, a plurality of FIFO (first in first out) registers, a crossbar operand multiplexor coupled, a floating point multiplier, and a floating point adder. The floating point multiplier and the floating point adder are disposed between the crossbar operand multiplexor and the product-terms and summation buses, and are in parallel to each other. The invention also provides the configuration register and the command register in order to provide flexible architecture and the capability to fine-tune the performance to a particular application. The invention performs the multiplication operation and the addition operation in a pipelined fashion. Once the pipeline is filled, the invention outputs one multiplication output and one addition output at each clock cycle. The invention reduces the latency of the pipelined operation and improves the overall system performance by separating the floating point multiplier from the floating point adder so that the multiplication operation can be executed separately and independently of the addition operation.

US Patent:

6938253, Aug 30, 2005

Filed:

May 2, 2001

Appl. No.:

09/847976

Inventors:

Jason Seung-Min Kim - San Jose CA, US

Assignee:

PortalPlayer, Inc. - Santa Clara CA

International Classification:

G06F009/46

US Classification:

718102, 718104, 718107

Abstract:

To facilitate inter-processor communication between multiple processors in a computer system and to enable the accessing of a dual port memory, or other system resources, without requiring the memory or the data/address bus to be locked, the present invention provides a semaphore unit that preferably incorporates a shared mailbox architecture that, in combination with a set of hardware semaphore registers, enables inter-process communication among the multi-processors. Cooperative multitasking may be accomplished through the use of shared mailbox communication protocols while a preemptive multitasking may be accomplished through the use of hardware semaphore registers.

US Patent:

6952749, Oct 4, 2005

Filed:

May 2, 2001

Appl. No.:

09/849885

Inventors:

Jason Seung-Min Kim - San Jose CA, US

Assignee:

PortalPlayer, Inc. - Santa Clara CA

International Classification:

G06F013/24

US Classification:

710260, 710269, 710 48

Abstract:

An interrupt handling system and method for a multiple processor system permit the interrupts generated by one or more hardware devices to be routed and prioritized dynamically. In particular, the interrupt controller permits the interrupts to be dynamically routed between the multiple processors and permits a particular interrupt to be dynamically assigned a priority level. The interrupt handling system also permits software based interrupts wherein, for example, one processor may interrupt another processor.

US Patent:

6990594, Jan 24, 2006

Filed:

May 2, 2001

Appl. No.:

09/847975

Inventors:

Jason Seung-Min Kim - San Jose CA, US

Assignee:

PortalPlayer, Inc. - San Jose CA

International Classification:

G06F 1/06

US Classification:

713322, 713501

Abstract:

A power management system and method permit the total power consumption by a portable electronic device to be reduced so that the portable electronic device has a longer operating time on a limited power source, such as a battery. The system may also be used with devices that are powered by a more permanent source of power. The system may combine static power management techniques as well as dynamic power management techniques. The system may include a flexible clock generator.

US Patent:

7177430, Feb 13, 2007

Filed:

Oct 31, 2001

Appl. No.:

10/000700

Inventors:

Jason Seung-Min Kim - San Jose CA, US

Assignee:

Portalplayer, Inc. - San Jose CA

International Classification:

H04K 1/02
H04N 7/167
G06K 9/36
G06K 9/46

US Classification:

380252, 380200, 382200

Abstract:

The present invention provides a system and method for introducing white noises into a digital audio signal so that there is progressive and cumulative degradation in audio quality after each successive reproduction of the audio sound signal in a fashion analogous to analog audio reproduction. The invention provides a white noise generator, and a digital entroping unit. In a preferred embodiment, the white noise generator is implemented by a hardware random number generator. The digital entroping unit controls the magnitude of white noise desired based on a random number generated by the random number generator, and adds the white noise to the input audio sound signal to produce a degraded audio sound signal. The magnitude of white noise can be controlled by using various masking and formatting of random number data.

US Patent:

7248597, Jul 24, 2007

Filed:

May 2, 2001

Appl. No.:

09/847963

Inventors:

Jason Seung-Min Kim - San Jose CA, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

H04L 12/28
G06F 3/00
G06F 7/38
H03K 19/173

US Classification:

370419, 370463, 326 38, 326 62, 710 8, 710 62

Abstract:

The present invention permits an I/O port to be used with a variety of different I/O devices, regardless of their device type implementation, such as tri-state I/O devices, pull-up I/O devices, or pull-down I/O devices. Thus, one set of pins may be used for various different I/O devices.