Jason Leonard

Address:

207 Matterhorne Trl, Moncure, NC 27559

VIN:

1GTEK19Z47Z139366

Make:

GMC

Model:

SIERRA 1500 CLASSIC

Year:

2007

US Patent:

7230497, Jun 12, 2007

Filed:

Jun 17, 2005

Appl. No.:

11/154548

Inventors:

Jason Leonard - San Mateo CA, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

H03L 7/00

US Classification:

331 16, 331 10, 331 1 R, 331108 C

Abstract:

System for controlling the frequency of an oscillator. A first circuit is coupled to the oscillator and arranged for receiving an externally provided clock signal at a first input node. A second circuit coupled to the oscillator is arranged for receiving an externally provided frequency reference input at a second input node. The first circuit uses the clock signal received at the first input node to control the frequency of the oscillator. In absence of a clock signal received at the first node, the second circuit uses the frequency reference input received at the second input node to control the frequency of the oscillator. The frequency reference input is selectively at one of (a) a first or second fixed voltage level designating a first or second oscillator frequency, and (b) a variable signal level designating a frequency between the first and second oscillator frequencies.

US Patent:

7386646, Jun 10, 2008

Filed:

Aug 25, 2005

Appl. No.:

11/213009

Inventors:

Kimming So - Palo Alto CA, US
Baobinh N. Truong - San Jose CA, US
Jason Leonard - San Jose CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 13/24

US Classification:

710260, 710267

Abstract:

A system and method for interrupt distribution in a multithread processor are disclosed. A connection between an interrupt and a set of thread processors can be programmed. When the interrupt is executed, the set of thread processors are affected. While executing the thread processor tasks, the connection may be reprogrammed to interrupt another set of thread processors.

US Patent:

7617380, Nov 10, 2009

Filed:

Aug 25, 2005

Appl. No.:

11/212950

Inventors:

Kimming So - Palo Alto CA, US
Jason Leonard - San Jose CA, US
Gurvinder S. Sareen - San Ramon CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 12/00
G06F 9/26
G06F 9/34

US Classification:

711207, 711203, 711205, 711206

Abstract:

A system and method for synchronizing translation lookaside buffer (TLB) access in a multithread processor is disclosed. When a first exception is found while searching the TLB, the exception is handled. While the exception is handled, thread processors are restricted from requesting the handling of any other exception.

US Patent:

7990120, Aug 2, 2011

Filed:

Aug 4, 2006

Appl. No.:

11/499005

Inventors:

Jason Leonard - Moncure NC, US
Joey Martin Esteves - Tracy CA, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

G05F 1/00
G05F 3/16

US Classification:

323282, 323224

Abstract:

Switching regulator circuits and methods are provided for regulating output voltage that include an adjustable minimum peak inductor current level and adjustable burst comparator hysteresis for Burst Mode operation in switching regulators. Control over minimum peak inductor current level and burst comparator hysteresis is achieved during Burst Mode operation by allowing external user control of the burst threshold level and the burst comparator hysteresis. A single user-accessible input pin, two user-accessible input pins, or three user-accessible input pins may be used to distinguish between forced continuous and Burst Mode operations, set a burst threshold level, and set a burst comparator hysteresis during Burst Mode operation. The present invention may be applied to buck, boost, buck-boost, or any other suitable regulator circuit configuration. The present invention also may be employed with synchronous and non-synchronous switching regulators.

US Patent:

8030907, Oct 4, 2011

Filed:

Nov 20, 2008

Appl. No.:

12/275129

Inventors:

Terry J Groom - Lucas TX, US
Jason Leonard - Moncure NC, US

Assignee:

Linear Technology Corporation - Milpitas CA

International Classification:

G05F 1/10
G05F 1/40

US Classification:

323222, 323285, 323290

Abstract:

A pulse generator circuit in a DC-to-DC converter may be configured to generate pulses that have a frequency that increases in response to increases in the load on the DC-to-DC converter. The pulse generator circuit may be configured to cause each pulse to have a constant width. When the pulse reaches the end of the constant width and the magnitude of the current through an inductance in the converter is less than a threshold value, however, the pulse generator may be configured to extend the pulse until the magnitude of the current through the inductance reaches the threshold value. The pulse generator circuit may be configured to prematurely terminate each pulse if and at such time as the load voltage exceeds a target value by approximately half of the peak-to-peak voltage of the ripple component plus the noise component margin.

US Patent:

20060224653, Oct 5, 2006

Filed:

Aug 25, 2005

Appl. No.:

11/212949

Inventors:

Kimming So - Palo Alto CA, US
Jason Leonard - San Jose CA, US
Philip Houghton - Surrey, CA
Henry Li - Vancouver, CA
Baobinh Truong - San Jose CA, US

International Classification:

G06F 7/38

US Classification:

708490000

Abstract:

A method and system for performing digital signal processing operations in a computer system are disclosed. In addition to the ability to perform DSP operation on a new hardware platform, this method and system allow the dynamic and global control of saturation and left shifting prior to accumulation.

US Patent:

20060224654, Oct 5, 2006

Filed:

Aug 25, 2005

Appl. No.:

11/217651

Inventors:

Kimming So - Palo Alto CA, US
Henry Li - Vancouver, CA
Jason Leonard - San Jose CA, US
Baobinh Truong - San Jose CA, US

International Classification:

G06F 7/38

US Classification:

708490000

Abstract:

A method and system for performing digital signal processing operations in a computer system are disclosed. Digital Signal Processing operations such as multiply and add (MADD) or multiply and subtract (MSUB) can be performed by general-purpose microprocessors. The DSP operations are directed to n-bit operands that are in m-bit registers. The register size (m) may be a multiple of the operand size (n). For example, the DSP operations may utilize 32-bit registers with 16-bit or 8-bit operands, or the DSP operations may utilize 64-bit registers with 32-bit, 16-bit, or 8-bit operands.

US Patent:

20070067778, Mar 22, 2007

Filed:

Aug 25, 2005

Appl. No.:

11/212958

Inventors:

Kimming So - Palo Alto CA, US
Jason Leonard - San Jose CA, US

International Classification:

G06F 9/46

US Classification:

719310000

Abstract:

A system and method for Inter-Thread Communication using software interrupts in a multithread processor are disclosed. Bits in a shared control register and/or a private control register can enable an Inter-Thread Communication path. When the interrupt is triggered, one thread processor raises an interrupt in another thread processor.