Jason C Lin

US Patent:

20130194250, Aug 1, 2013

Filed:

Jan 31, 2013

Appl. No.:

13/755111

Inventors:

E INK CORPORATION - Cambridge MA, US
Matthew J. Aprea - Wellesley MA, US
Kenneth R. Crounse - Somerville MA, US
Demetrious Mark Harrington - Dartmouth MA, US
Jason Lin - Malden MA, US
Theodore A. Sjodin - Lexington MA, US
Chia-Chen Su - Cambridge MA, US

Assignee:

E INK CORPORATION - Cambridge MA

International Classification:

G09G 3/34

US Classification:

345212, 345107

Abstract:

A variety of methods for driving electro-optic displays so as to reduce visible artifacts are described. Such methods include (a) applying a first drive scheme to a non-zero minor proportion of the pixels of the display and a second drive scheme to the remaining pixels, the pixels using the first drive scheme being changed at each transition; (b) using two different drive schemes on different groups of pixels so that pixels in differing groups undergoing the same transition will not experience the same waveform; (c) applying either a balanced pulse pair or a top-off pulse to a pixel undergoing a white-to-white transition and lying adjacent a pixel undergoing a visible transition; (d) driving extra pixels where the boundary between a driven and undriven area would otherwise fall along a straight line; and (e) driving a display with both DC balanced and DC imbalanced drive schemes, maintaining an impulse bank value for the DC imbalance and modifying transitions to reduce the impulse bank value.

US Patent:

20130321278, Dec 5, 2013

Filed:

May 21, 2013

Appl. No.:

13/898592

Inventors:

Yuval Ben-Dov - Cambridge MA, US
Kenneth R. Crounse - Somerville MA, US
Jason Lin - Malden MA, US
Karl Raymond Amundson - Cambridge MA, US
Michael Patrick Almon - Brighton MA, US
Hugh M. Enxing - Medford MA, US

Assignee:

E INK CORPORATION - Cambridge MA

International Classification:

G06F 3/042
G06F 3/02

US Classification:

345168, 345175

Abstract:

A touch screen electro-optic display is arranged such that upon a touch being detected on the display surface, the display surface surrounding the touch “blinks” by being driven to a different optical state, then back to its original state. A second method uses a display having a pen or stylus which can draw lines upon the display. A first line segment is detected and its area updated using a first drive scheme having short waveforms. The area of a second line segment is updated using the first drive scheme. Thereafter, the areas of both line segments are updated using a second drive scheme different from the first drive scheme.

US Patent:

20220415268, Dec 29, 2022

Filed:

Aug 30, 2022

Appl. No.:

17/899283

Inventors:

- Billerica MA, US
Matthew J. APREA - Wellesley MA, US
Kenneth R. CROUNSE - Somerville MA, US
Demetrious Mark HARRINGTON - Cambridge MA, US
Jason LIN - Malden MA, US
Theodore A. SJODIN - Lexington MA, US
Chia-Chen SU - San Francisco CA, US

International Classification:

G09G 3/34

Abstract:

A variety of methods for driving electro-optic displays so as to reduce visible artifacts are described. Such methods include (a) applying a first drive scheme to a non-zero minor proportion of the pixels of the display and a second drive scheme to the remaining pixels, the pixels using the first drive scheme being changed at each transition; (b) using two different drive schemes on different groups of pixels so that pixels in differing groups undergoing the same transition will not experience the same waveform; (c) applying either a balanced pulse pair or a top-off pulse to a pixel undergoing a white-to-white transition and lying adjacent a pixel undergoing a visible transition; (d) driving extra pixels where the boundary between a driven and undriven area would otherwise fall along a straight line; and (e) driving a display with both DC balanced and DC imbalanced drive schemes, maintaining an impulse bank value for the DC imbalance and modifying transitions to reduce the impulse bank value.

US Patent:

20220214882, Jul 7, 2022

Filed:

Mar 23, 2022

Appl. No.:

17/702714

Inventors:

- Redmond WA, US
Gregory John COLOMBO - Kirkland WA, US
Weidong CUI - Redmond WA, US
Jason LIN - Bellevue WA, US
Kenneth Dean JOHNSON - Bellevue WA, US

International Classification:

G06F 9/38
G06F 11/36

Abstract:

A program is executed using a call stack and shadow stack. The call stack includes frames having respective return addresses. The frames may also store variables and/or parameters. The shadow stack stores duplicates of the return addresses in the call stack. The call stack and the shadow stack are maintained by, (i) each time a function is called, adding a corresponding stack frame to the call stack and adding a corresponding return address to the shadow stack, and (ii) each time a function is exited, removing a corresponding frame from the call stack and removing a corresponding return address from the shadow stack. A backtrace of the program's current call chain is generated by accessing the return addresses in the shadow stack. The outputted backtrace includes the return addresses from the shadow stack and/or information about the traced functions that is derived from the shadow stack's return addresses.

US Patent:

20230088081, Mar 23, 2023

Filed:

Sep 17, 2021

Appl. No.:

17/489390

Inventors:

- Redmond WA, US
Jason LIN - Bellevue WA, US
Matthew John WOOLMAN - Seattle WA, US
Mehmet IYIGUN - Kirkland WA, US

International Classification:

G06F 21/52
G06F 12/10

Abstract:

Handling a memory fault based on detecting whether a memory pointer was invalidated by a pointer authentication (PA) failure. After an access to a memory pointer causes a memory fault, detecting that the memory pointer was invalidated by a PA failure includes creating a new memory pointer by replacing reserved bits of the memory pointer with a default value, and determining that the new memory pointer corresponds to a memory address that falls within executable memory. This determination includes determining that the memory address is within an executable memory page, determining that a call instruction is stored at a prior memory address that immediately precedes the memory address, and/or determining that the memory address corresponds to a code section of an executable file. The PA failure is handled based on logging the PA failure, terminating the application program, and/or resuming execution at an instruction stored at the memory address.

US Patent:

20210375217, Dec 2, 2021

Filed:

Jul 30, 2021

Appl. No.:

17/389886

Inventors:

- Billerica MA, US
Matthew J. APREA - Wellesley MA, US
Kenneth R. CROUNSE - Somerville MA, US
Demetrious Mark HARRINGTON - Cambridge MA, US
Jason LIN - Malden MA, US
Theodore A. SJODIN - Lexington MA, US
Chia-Chen SU - San Francisco CA, US

International Classification:

G09G 3/34

Abstract:

A variety of methods for driving electro-optic displays so as to reduce visible artifacts are described. Such methods include (a) applying a first drive scheme to a non-zero minor proportion of the pixels of the display and a second drive scheme to the remaining pixels, the pixels using the first drive scheme being changed at each transition; (b) using two different drive schemes on different groups of pixels so that pixels in differing groups undergoing the same transition will not experience the same waveform; (c) applying either a balanced pulse pair or a top-off pulse to a pixel undergoing a white-to-white transition and lying adjacent a pixel undergoing a visible transition; (d) driving extra pixels where the boundary between a driven and undriven area would otherwise fall along a straight line; and (e) driving a display with both DC balanced and DC imbalanced drive schemes, maintaining an impulse bank value for the DC imbalance and modifying transitions to reduce the impulse bank value.

US Patent:

20210311740, Oct 7, 2021

Filed:

Jun 19, 2021

Appl. No.:

17/352283

Inventors:

- Redmond WA, US
Mehmet IYIGUN - Kirkland WA, US
Jason LIN - Bellevue WA, US
Matthew John WOOLMAN - Seattle WA, US

International Classification:

G06F 9/30
G06F 9/38
G06F 9/50

Abstract:

Performing shadow stack functionality for a thread in an audit mode includes initiating execution of a thread at the processor. Execution of the thread includes initiating execution of executable code of an application binary as part of the thread and enabling shadow stack functionality for the thread in an audit mode. Based at least on the execution of the thread in the audit mode, at least a portion of the shadow stack is enabled to be a circular stack. In response to determining that usage of the shadow stack has reached the defined threshold, one or more currently used entries of the shadow stack are overwritten, preventing the shadow stack from overflowing.

US Patent:

20210303681, Sep 30, 2021

Filed:

Jul 31, 2020

Appl. No.:

16/945458

Inventors:

- Redmond WA, US
Jason LIN - Bellevue WA, US
Niraj MAJMUDAR - Renton WA, US
Mehmet IYIGUN - Kirkland WA, US

International Classification:

G06F 21/54
G06F 9/48
G06F 9/445

Abstract:

Enforcing shadow stack violations for dynamic code. A thread is executed at a processor, which includes generating a portion of dynamic code for execution by the thread, identifying a range of memory addresses where the portion of dynamic code is loaded in memory, and initiating execution of the portion of dynamic code. Based at least on execution of the thread, an exception triggered by a mismatch between a first return address popped from a call stack corresponding to the thread and a second return address popped from a shadow stack corresponding to the thread is processed. Processing the exception includes (i) determining whether the second return address popped from the shadow stack is within the identified range of addresses, and (ii) based on having determined that the second return address is within the range of addresses, initiating a shadow stack enforcement action.