Jason Y Lin

US Patent:

20220214882, Jul 7, 2022

Filed:

Mar 23, 2022

Appl. No.:

17/702714

Inventors:

- Redmond WA, US
Gregory John COLOMBO - Kirkland WA, US
Weidong CUI - Redmond WA, US
Jason LIN - Bellevue WA, US
Kenneth Dean JOHNSON - Bellevue WA, US

International Classification:

G06F 9/38
G06F 11/36

Abstract:

A program is executed using a call stack and shadow stack. The call stack includes frames having respective return addresses. The frames may also store variables and/or parameters. The shadow stack stores duplicates of the return addresses in the call stack. The call stack and the shadow stack are maintained by, (i) each time a function is called, adding a corresponding stack frame to the call stack and adding a corresponding return address to the shadow stack, and (ii) each time a function is exited, removing a corresponding frame from the call stack and removing a corresponding return address from the shadow stack. A backtrace of the program's current call chain is generated by accessing the return addresses in the shadow stack. The outputted backtrace includes the return addresses from the shadow stack and/or information about the traced functions that is derived from the shadow stack's return addresses.

US Patent:

20230088081, Mar 23, 2023

Filed:

Sep 17, 2021

Appl. No.:

17/489390

Inventors:

- Redmond WA, US
Jason LIN - Bellevue WA, US
Matthew John WOOLMAN - Seattle WA, US
Mehmet IYIGUN - Kirkland WA, US

International Classification:

G06F 21/52
G06F 12/10

Abstract:

Handling a memory fault based on detecting whether a memory pointer was invalidated by a pointer authentication (PA) failure. After an access to a memory pointer causes a memory fault, detecting that the memory pointer was invalidated by a PA failure includes creating a new memory pointer by replacing reserved bits of the memory pointer with a default value, and determining that the new memory pointer corresponds to a memory address that falls within executable memory. This determination includes determining that the memory address is within an executable memory page, determining that a call instruction is stored at a prior memory address that immediately precedes the memory address, and/or determining that the memory address corresponds to a code section of an executable file. The PA failure is handled based on logging the PA failure, terminating the application program, and/or resuming execution at an instruction stored at the memory address.

US Patent:

20210311740, Oct 7, 2021

Filed:

Jun 19, 2021

Appl. No.:

17/352283

Inventors:

- Redmond WA, US
Mehmet IYIGUN - Kirkland WA, US
Jason LIN - Bellevue WA, US
Matthew John WOOLMAN - Seattle WA, US

International Classification:

G06F 9/30
G06F 9/38
G06F 9/50

Abstract:

Performing shadow stack functionality for a thread in an audit mode includes initiating execution of a thread at the processor. Execution of the thread includes initiating execution of executable code of an application binary as part of the thread and enabling shadow stack functionality for the thread in an audit mode. Based at least on the execution of the thread in the audit mode, at least a portion of the shadow stack is enabled to be a circular stack. In response to determining that usage of the shadow stack has reached the defined threshold, one or more currently used entries of the shadow stack are overwritten, preventing the shadow stack from overflowing.

US Patent:

20210303681, Sep 30, 2021

Filed:

Jul 31, 2020

Appl. No.:

16/945458

Inventors:

- Redmond WA, US
Jason LIN - Bellevue WA, US
Niraj MAJMUDAR - Renton WA, US
Mehmet IYIGUN - Kirkland WA, US

International Classification:

G06F 21/54
G06F 9/48
G06F 9/445

Abstract:

Enforcing shadow stack violations for dynamic code. A thread is executed at a processor, which includes generating a portion of dynamic code for execution by the thread, identifying a range of memory addresses where the portion of dynamic code is loaded in memory, and initiating execution of the portion of dynamic code. Based at least on execution of the thread, an exception triggered by a mismatch between a first return address popped from a call stack corresponding to the thread and a second return address popped from a shadow stack corresponding to the thread is processed. Processing the exception includes (i) determining whether the second return address popped from the shadow stack is within the identified range of addresses, and (ii) based on having determined that the second return address is within the range of addresses, initiating a shadow stack enforcement action.

US Patent:

20210224900, Jul 22, 2021

Filed:

Apr 2, 2021

Appl. No.:

17/221268

Inventors:

- Frankfurt am Main, DE
Arvind Kumar Rai - Harrison NJ, US
Bharat Gopalan - New York NY, US
Young Been Eom - River Vale NJ, US
Dwight Silvera - Newburgh NY, US
Brandon Von-Feldt - New York NY, US
Monojit Mitra - Stamford CT, US
Laura Bertarelli - New York NY, US
Rajneesh Acharya - Princeton Junction NJ, US
Seth Lipschitz - Tenafly NJ, US
Jason Lin - Syosset NY, US
Patricia M. Gavin - Brooklyn NY, US
Ronakkumar S. Patel - Edison NJ, US

International Classification:

G06Q 40/02
G06N 20/00

Abstract:

A method and product designed for preferably creating, validating and executing regression based models and calculations for Stress Testing and Entity Planning purposes is provided covering model execution life-cycle details from model creation, validation, and execution. The preferred embodiments include a self-service regression based model configuration and creation with workflow approval tool called a model wizard; a central standardized I/O data interface called ODS to receive and store quarterly historical and spot financial market information, and reference data used as model input, and to store model output(s) in the preferred form of quarterly base and stress projections; a java based execution engine to run the approved models from the repository with ability to apply model adjustments; a web-based user interface to view the model lineage, input, equations in mathematical form using MathJax and the output.

US Patent:

20210109795, Apr 15, 2021

Filed:

Oct 11, 2019

Appl. No.:

16/599195

Inventors:

- Redmond WA, US
Rahul NAIR - Bellevue WA, US
Mark Allan BELLON - Seattle WA, US
Christopher Peter KLEYNHANS - Bothell WA, US
Jason LIN - Bellevue WA, US
Ojasvi CHOUDHARY - Seattle WA, US
Tristan Anthony BROWN - Seattle WA, US

Assignee:

Microsoft Technology Licensing, LLC - Redmond WA

International Classification:

G06F 9/50
G06F 9/48

Abstract:

Described herein is a system and method for latency-aware thread scheduled. For each processor core, an estimated cost to schedule a particular thread on the processor core is calculated. The estimated cost to schedule can be a period of time between the scheduling decision and the point in time where the scheduled thread begins to run. For each processor core, an estimated cost to execute the particular thread on the processor core is calculated. The estimated cost to execute can be a period of time spent actually running the particular thread on a particular processor core. A determination as to which processor core to utilize for execution of the particular thread based, at least in part, upon the calculated estimated costs to schedule the particular thread and/or the calculated estimated costs to execute the particular thread. The particular thread can be scheduled to execute on the determined processor core.

US Patent:

20210011717, Jan 14, 2021

Filed:

Sep 29, 2020

Appl. No.:

17/037605

Inventors:

- Redmond WA, US
Jason LIN - Bellevue WA, US
Niraj MAJMUDAR - Renton WA, US
Mehmet IYIGUN - Kirkland WA, US

International Classification:

G06F 9/30
G06F 9/32

Abstract:

A verified stack trace can be generated by utilizing information contained in a shadow stack, such as a hardware protected duplicate stack implemented for malware prevention and computer security. The shadow stack contains return addresses which are obtainable without requiring an unwinding of the traditional call stack. As such, triaging based on return address information can be performed more quickly and more efficiently, and with a reduced utilization of processing resources. Additionally, the generation of a verified stack trace can be performed, with such a verified stack trace containing return addresses that are known to be correct and not corrupted. The return addresses can either be read from the traditional call stack, or derived therefrom, and then verified by comparison to corresponding return addresses from the shadow stack, or they can be read directly from the shadow stack.

US Patent:

20200371809, Nov 26, 2020

Filed:

May 20, 2019

Appl. No.:

16/417493

Inventors:

- Redmond WA, US
Gregory John COLOMBO - Kirkland WA, US
Weidong CUI - Redmond WA, US
Jason LIN - Bellevue WA, US
Kenneth Dean JOHNSON - Bellevue WA, US

International Classification:

G06F 9/38
G06F 11/36

Abstract:

A program is executed using a call stack and shadow stack. The call stack includes frames having respective return addresses. The frames may also store variables and/or parameters. The shadow stack stores duplicates of the return addresses in the call stack. The call stack and the shadow stack are maintained by, (i) each time a function is called, adding a corresponding stack frame to the call stack and adding a corresponding return address to the shadow stack, and (ii) each time a function is exited, removing a corresponding frame from the call stack and removing a corresponding return address from the shadow stack. A backtrace of the program's current call chain is generated by accessing the return addresses in the shadow stack. The outputted backtrace includes the return addresses from the shadow stack and/or information about the traced functions that is derived from the shadow stack's return addresses.