Jason A Porter

US Patent:

7284231, Oct 16, 2007

Filed:

Dec 21, 2004

Appl. No.:

11/018637

Inventors:

Kevin D. Lucas - Meylan, FR
Robert E. Boone - Grenoble, FR
Mehul D. Shroff - Austin TX, US
Kirk J. Strozewski - Round Rock TX, US
Chi-Min Yuan - Austin TX, US
Jason T. Porter - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G06F 17/50

US Classification:

716 21, 716 19

Abstract:

A method for improving manufacturability of a design includes performing space or enclosure checks on multiple interacting layers of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.

US Patent:

20120329234, Dec 27, 2012

Filed:

Jun 22, 2011

Appl. No.:

13/166561

Inventors:

Jason T. Porter - Austin TX, US
Dmitri Kulik - Cedar Park TX, US

International Classification:

H01L 21/336

US Classification:

438303, 257E21409

Abstract:

A method includes forming a gate over a substrate having a semiconductor layer comprising silicon. The gate has a sidewall spacer on sides of the gate. The gate has a gate length less than or equal to 50 nanometers. The gate is formed of polysilicon. A cobalt layer is formed on a top of the gate and the sidewall spacer. A titanium nitride layer is formed on the cobalt layer. The titanium nitride layer has a thickness over the gate in a range of 10 to 14 nanometers. An anneal is performed to form a cobalt silicide layer on the top of the gate and leave cobalt on the sidewall spacer. An etchant is applied that etches cobalt and titanium nitride selective to cobalt silicide to the titanium nitride layer. The cobalt is on the sidewall spacer and the cobalt silicide layer. An anneal is performed to increase conductivity of the cobalt silicide layer.