Jason A Ross

US Patent:

7468904, Dec 23, 2008

Filed:

Feb 23, 2007

Appl. No.:

11/678097

Inventors:

David C. Lawson - Haymarket VA, US
Jason Ross - Fairfax VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

G11C 11/00

US Classification:

365154, 365148, 365149

Abstract:

A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first inverter and a second inverter connected to each other in a cross-coupled manner. The SEU hardened memory cell also includes a first resistor, a second resistor and a capacitor. The first resistor is connected between an input of the first inverter and an output of the second inverter. The second resistor is connected between an input of the second inverter and an output of the first inverter. The capacitor is connected between an input of the first inverter and an input of the second inverter.

US Patent:

8189367, May 29, 2012

Filed:

Feb 8, 2008

Appl. No.:

12/028042

Inventors:

David C. Lawson - Haymarket VA, US
Jason F. Ross - Fairfax VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

G11C 11/00

US Classification:

365154, 365156, 365149, 365 72, 365188

Abstract:

A single event upset (SEU) hardened memory cell to be utilized in static random access memories is disclosed. The SEU hardened memory cell includes a first transistor, a second transistor and a first resistor connected between a source of the first transistor and a drain of the second transistor. The SEU hardened memory cell also includes a third transistor, a fourth transistor and a second resistor connected between a source of the third transistor and a drain of the fourth transistor. The first resistor is also connected between a gate of the third transistor and the drain of the second transistor. The second resistor is also connected between a gate of the first transistor and the drain of the fourth transistor.

US Patent:

20140017872, Jan 16, 2014

Filed:

Jul 12, 2012

Appl. No.:

13/547571

Inventors:

JASON F. ROSS - HAYMARKET VA, US
CHI-HUA YANG - MANASSAS VA, US
THOMAS J. McINTYRE - NOKESVILLE VA, US

Assignee:

BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC. - Nashua NH

International Classification:

H01L 21/02

US Classification:

438381, 257E21011

Abstract:

A method for fabricating a metal-insulator-metal capacitor (MIMCap) is disclosed. A first metal layer is provided on top of an oxide layer. A nitride layer is then deposited on the first metal layer. The nitride layer and the first metal layer are etched to form a MIMCap metal layer. The gaps among the MIMCap metal layer are filled with a plasma oxide, and the excess plasma oxide is polished using the nitride layer a polish stop. After removing the nitride layer, a dielectric layer and a second metal layer are deposited on the MIMCap metal layer. Finally, the dielectric layer and the second metal layer are etched to form a set of MIMCap structures.

US Patent:

20200379842, Dec 3, 2020

Filed:

May 29, 2019

Appl. No.:

16/425377

Inventors:

- Nashua NH, US
Jason F. Ross - Haymarket VA, US

Assignee:

BAE SYSTEMS Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

G06F 11/10
G11C 11/56
G11C 11/16
G06F 1/3206
G06F 1/3287

Abstract:

A disclosed apparatus and method reduce the likelihood of multiple bit single event upset (SEU) errors in space-deployed memory devices and memory macros, without requiring novel, specialized memory designs and without significant added cost or performance loss. For each memory, a bit selection layer effectively increases the mux of the memory bit table, thereby reducing the word size while increasing the word capacity, without changing the total memory capacity. As a result, the separation between the physical bit storage locations for each word is increased, thereby reducing the likelihood of multiple bit SEU errors. A buffer can be implemented if the memory lacks individual bit write control. The memory can be implemented in a core IC of an MCM-HIC, and the bit selection layer and/or buffer can be implemented in a chiplet or chiplets of the MCM-HIC.

US Patent:

20200105360, Apr 2, 2020

Filed:

Sep 28, 2018

Appl. No.:

16/146650

Inventors:

- NASHUA NH, US
JASON F. ROSS - HAYMARKET VA, US
KEVIN LINGER - ARLINGTON VA, US

International Classification:

G11C 29/32
G11C 7/22
G11C 7/10

Abstract:

A scannable-latch random access memory (SLRAM) is disclosed. The SLRAM includes two rows of memory cells. The SLRAM includes a functional data input, a scan data input, a first and second functional data outputs, a scan data output, and a scan enable. The functional data input is connected to a first memory cell in a first and second rows of memory cells. The scan data input is connected to the first memory cell in the first or second row of memory cells. The first and second functional data outputs are connected to a last memory cell in the first and second row of memory cells, respectively. The scan data output is connected to the last memory cell in the first or second row of memory cells. The scan enable allows data to be output from the scan data output or the first and second functional data outputs.

US Patent:

20200051961, Feb 13, 2020

Filed:

Aug 7, 2018

Appl. No.:

16/057204

Inventors:

- Nashua NH, US
Jason F. Ross - Haymarket VA, US
John T. Matta - Nokesville VA, US
Richard J. Ferguson - Bealeton VA, US
Alan F. Dennis - Chantilly VA, US
Daniel L. Stanley - Warrenton VA, US

International Classification:

H01L 25/16
H01L 23/498
H01L 23/00
H01L 27/112
H01L 25/00

Abstract:

An MCM-HIC device flexibly adds enhanced features to a VLSI “core” IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one “chiplet” that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or “mixed” chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.

US Patent:

20200043121, Feb 6, 2020

Filed:

Jul 31, 2018

Appl. No.:

16/050431

Inventors:

- Santa Clara CA, US
Sang-hee Lee - San Jose CA, US
Scott Janus - Loomis CA, US
Stanley Baran - Chandler AZ, US
Michael Apodaca - Folsom CA, US
Prasoonkumar Surti - Folsom CA, US
Srikanth Potluri - Folsom CA, US
Atsuo Kuwahara - Portland OR, US
Kai Xiao - San Jose CA, US
Jason Tanner - Folsom CA, US
Gokcen Cilingir - San Jose CA, US
Archie Sharma - Folsom CA, US
Jeffrey Tripp - Hillsboro OR, US
Jason Ross - Folsom CA, US
Barnan Das - Newark CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06T 7/20
G06T 15/00
G06T 5/20
H04N 19/517
H04N 19/523

Abstract:

An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to decode occupancy map data and auxiliary patch information and generate a plurality of patch video frames based on patch data decoded from the occupancy map data and auxiliary patch information, and a memory communicatively coupled to the one or more processors.

US Patent:

20200043182, Feb 6, 2020

Filed:

Jul 31, 2018

Appl. No.:

16/050468

Inventors:

- Santa Clara CA, US
Barnan Das - Newark CA, US
Hugues Labbe - Granite Bay CA, US
Jong Dae Oh - San Jose CA, US
Gokcen Cilingir - San Jose CA, US
James Holland - Folsom CA, US
Narayan Biswal - Folsom CA, US
Yi-Jen Chiu - San Jose CA, US
Qian Xu - Folsom CA, US
Mayuresh Varerkar - Folsom CA, US
Sang-Hee Lee - San Jose CA, US
Stanley Baran - Chandler AZ, US
Srikanth Potluri - Folsom CA, US
Jason Ross - Folsom CA, US
Maruthi Sandeep Maddipatla - Sacramento CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 7/262
G06T 3/40
G06T 7/30
G06T 15/08
G06T 17/00

Abstract:

Embodiments described herein provide an apparatus comprising a processor to divide a first point cloud data set frame representing a three dimensional space at a first point in time into a matrix of blocks, determine at least one three dimensional (3D) motion vector for at least a subset of blocks in the matrix of blocks, generate a predicted second point cloud data set frame representing a prediction of the three dimensional space at a second point in time by applying the at least one 3D motion vector to the subset of blocks in the matrix of blocks, compare the predicted second point cloud data set frame to a second point cloud data set frame representing a prediction of the three dimensional space at a second point in time to generate a prediction error parameter, and encode the second point cloud data set frame as a function of the first point cloud data set frame and the at least one three dimensional (3D) motion vector when the prediction error factor is beneath an error threshold to produce an encoded second point cloud data set frame. Other embodiments may be described and claimed.