Jason Eugene Stephens

US Patent:

20190267281, Aug 29, 2019

Filed:

May 14, 2019

Appl. No.:

16/411775

Inventors:

- GRAND CAYMAN, KY
Martin J. O'TOOLE - Saratoga Springs NY, US
Terry A. SPOONER - Mechanicville NY, US
Jason E. STEPHENS - Menands NY, US

International Classification:

H01L 21/768
H01L 23/528
H01L 21/033
H01L 23/522

Abstract:

The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.

US Patent:

20190221474, Jul 18, 2019

Filed:

Jan 16, 2018

Appl. No.:

15/872314

Inventors:

- Grand Cayman, KY
Martin J. O'TOOLE - Saratoga Springs NY, US
Terry A. SPOONER - Mechanicville NY, US
Jason E. STEPHENS - Menands NY, US

International Classification:

H01L 21/768
H01L 23/522
H01L 23/528
H01L 21/033

Abstract:

The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.

US Patent:

20180033701, Feb 1, 2018

Filed:

Oct 9, 2017

Appl. No.:

15/728445

Inventors:

- GRAND CAYMAN, KY
Tuhin Guha Neogi - Fishkill NY, US
Andy Chi-Hung Wei - Queensbury NY, US
Jia Zeng - Sunnyvale CA, US
Jongwook Kye - Sunnyvale CA, US
Jason Eugene Stephens - Menands NY, US
Irene Yuh-Ling Lin - Los Altos CA, US
Sudharshanan Raghunathan - Mechanicville NY, US
Lei Yuan - Cupertino CA, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman

International Classification:

H01L 21/8238
H01L 23/535
H01L 21/027
G06F 17/50
H01L 21/768
H01L 21/285
H01L 27/092
H01L 21/8234

Abstract:

At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

US Patent:

20170309560, Oct 26, 2017

Filed:

Apr 22, 2016

Appl. No.:

15/136384

Inventors:

- Grand Cayman, KY
Jason Eugene STEPHENS - Menands NY, US
Tuhin GUHA NEOGI - Clifton Park NY, US
Kai SUN - Clifton Park NY, US
Deniz Elizabeth CIVAY - Clifton Park NY, US
David Charles PRITCHARD - Glenville NY, US
Andy WEI - Kanata, CA

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 23/528
H01L 21/768
H01L 21/768
H01L 21/768
H01L 21/768
H01L 21/762
H01L 21/3213
H01L 21/311
H01L 21/311
H01L 23/522
H01L 21/033

Abstract:

Semiconductor devices and methods of fabricating the semiconductor devices with cross coupled contacts using patterning for cross couple pick-up are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a first lithography to pattern a first shape; performing a second lithography to pattern a second shape overlapping a portion of the first shape; processing the first shape and the second shape to form an isolation region at the overlap; and forming four regions separated by the isolation region. An intermediate semiconductor device is also disclosed.

US Patent:

20170263506, Sep 14, 2017

Filed:

Mar 11, 2016

Appl. No.:

15/067953

Inventors:

- Grand Cayman, KY
Tuhin Guha Neogi - Fishkill NY, US
Andy Chi-Hung Wei - Queensbury NY, US
Jia Zeng - Sunnyvale CA, US
Jongwook Kye - Sunnyvale CA, US
Jason Eugene Stephens - Menands NY, US
Irene Yuh-Ling Lin - Los Altos CA, US
Sudharshanan Raghunathan - Santa Clara CA, US
Lei Yuan - Cupertino CA, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman

International Classification:

H01L 21/8238
H01L 21/768
G06F 17/50
H01L 21/027
H01L 27/092
H01L 23/535
H01L 21/8234
H01L 21/285

Abstract:

At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

US Patent:

20170250080, Aug 31, 2017

Filed:

Feb 25, 2016

Appl. No.:

15/053818

Inventors:

- Grand Cayman, KY
Jason Eugene STEPHENS - Menands NY, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 21/033
H01L 23/532
H01L 23/522
H01L 21/768
H01L 23/528

Abstract:

A hard mask is formed into lines and bridges two adjacent lines using mandrels, spacers for the mandrels and a lithographic process for each bridge to create a metal line pattern in a layer of an interconnect structure with a line pitch below lithographic resolution.

US Patent:

20170221886, Aug 3, 2017

Filed:

Apr 18, 2017

Appl. No.:

15/490702

Inventors:

- GRAND CAYMAN, KY
Guillaume Bouche - Malta NY, US
Mark A. Zaleski - Malta NY, US
Tuhin Guha Neogi - Hopewell Junction NY, US
Jason E. Stephens - Hopewell Junction NY, US
Jongwook Kye - Sunnyvale CA, US
Jia Zeng - Sunnyvale CA, US

International Classification:

H01L 27/088
H01L 21/8238
H01L 27/092
H01L 21/8234
H01L 23/528
H01L 23/532

Abstract:

Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

US Patent:

20160300754, Oct 13, 2016

Filed:

Apr 13, 2015

Appl. No.:

14/684949

Inventors:

- Grand Cayman, KY
Jason Eugene Stephens - Albany NY, US
Jiong Li - Clifton Park NY, US
Guillaume Bouche - Albany NY, US
Richard A. Farrell - Albany NY, US

International Classification:

H01L 21/768

Abstract:

Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.