Jason B Stephens

US Patent:

20180182507, Jun 28, 2018

Filed:

Dec 20, 2017

Appl. No.:

15/848240

Inventors:

- Atlanta GA, US
David Marshall Cain - Easley SC, US
Matthew Leach - Fort Wayne IN, US
Christopher Richardson - Fort Wayne IN, US
Jason Dennis Stephens - Fort Wayne IN, US

International Classification:

H01B 7/00
H02K 3/04
H01F 27/28
H01F 27/34
H02K 3/42

Abstract:

A continuously transposed conductor (CTC) cable may include a plurality of electrically insulated strands arranged in two stacks with the plurality of strands successively transposed between the two stacks. Each strand may include a conductor and insulation formed at least partially around the conductor. Additionally, each strand may have a cross-sectional area that is less than approximately 0.0030 square inches. As a result, the CTC cable may be suitable for use in electrical devices relatively smaller than those associated with conventional CTC cables.

US Patent:

20180033701, Feb 1, 2018

Filed:

Oct 9, 2017

Appl. No.:

15/728445

Inventors:

- GRAND CAYMAN, KY
Tuhin Guha Neogi - Fishkill NY, US
Andy Chi-Hung Wei - Queensbury NY, US
Jia Zeng - Sunnyvale CA, US
Jongwook Kye - Sunnyvale CA, US
Jason Eugene Stephens - Menands NY, US
Irene Yuh-Ling Lin - Los Altos CA, US
Sudharshanan Raghunathan - Mechanicville NY, US
Lei Yuan - Cupertino CA, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman

International Classification:

H01L 21/8238
H01L 23/535
H01L 21/027
G06F 17/50
H01L 21/768
H01L 21/285
H01L 27/092
H01L 21/8234

Abstract:

At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

US Patent:

20170263506, Sep 14, 2017

Filed:

Mar 11, 2016

Appl. No.:

15/067953

Inventors:

- Grand Cayman, KY
Tuhin Guha Neogi - Fishkill NY, US
Andy Chi-Hung Wei - Queensbury NY, US
Jia Zeng - Sunnyvale CA, US
Jongwook Kye - Sunnyvale CA, US
Jason Eugene Stephens - Menands NY, US
Irene Yuh-Ling Lin - Los Altos CA, US
Sudharshanan Raghunathan - Santa Clara CA, US
Lei Yuan - Cupertino CA, US

Assignee:

GLOBALFOUNDRIES INC. - Grand Cayman

International Classification:

H01L 21/8238
H01L 21/768
G06F 17/50
H01L 21/027
H01L 27/092
H01L 23/535
H01L 21/8234
H01L 21/285

Abstract:

At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

US Patent:

20170263715, Sep 14, 2017

Filed:

Mar 11, 2016

Appl. No.:

15/067540

Inventors:

- Grand Cayman KY, US
Tuhin Guha Neogi - Fishkill NY, US
Sudharshanan Raghunathan - Santa Clara CA, US
Andy Chi-Hung Wei - Queensbury NY, US
Jason Eugene Stephens - Hopewell Junction NY, US
Vikrant Kumar Chauhan - Clifton Park NY, US
David Michael Permana - Ballston Spa NY, US

International Classification:

H01L 29/40
H01L 29/66
H01L 21/768
H01L 21/02
H01L 21/3105
H01L 21/027
H01L 29/49
H01L 21/311

Abstract:

At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.