Jason D Stevens

US Patent:

6741500, May 25, 2004

Filed:

Oct 4, 2002

Appl. No.:

10/264756

Inventors:

Daran DeShazo - Dallas TX
Agustinus Sutandi - Murphy TX
Jason Stevens - Plano TX

Assignee:

HPL Technologies, Inc. - San Jose CA

International Classification:

G11C 1600

US Classification:

36518528, 365104, 365154, 36518507

Abstract:

An OTP bit cell includes a latch circuit of cross-coupled inverters. A floating gate PMOS transistor is inserted in each of the inverters. One or the other of the floating gate PMOS transistors is programmed through an included programming circuit so that a differential output of the latch circuit provides a corresponding logic state that is the same each time when read. To program a selected floating gate PMOS transistor, appropriate write inputs are applied to the programming circuit while a high reference voltage to the OTP bit cell is raised to a level such that the selected floating gate PMOS transistor is programmed.

US Patent:

62227866, Apr 24, 2001

Filed:

Nov 2, 1999

Appl. No.:

9/432307

Inventors:

Wayland Bart Holland - Dallas TX
Craig Waller - Garland TX
Jason Stevens - Plano TX
Gary Johnson - Melissa TX

Assignee:

Silicon Aquarius, Inc.

International Classification:

G11C 700

US Classification:

365222

Abstract:

A dynamic random access memory 400 includes an array 401 of physical rows and columns of memory cells, the cells of each row coupled to first and second wordlines 603 and first and second bitlines 602. A direct input/output data path 402 having a width equal to a width of the rows supports simultaneous writing to each of the cells along a selected row using the first wordlines and first bitlines during a single access cycle without restore.