Jason Cheng Su

US Patent:

7596012, Sep 29, 2009

Filed:

Nov 8, 2007

Appl. No.:

11/937350

Inventors:

Jason T. Su - Los Altos CA, US
Karthik Swaminathan - San Jose CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G11C 11/40

US Classification:

365154, 365226, 365227

Abstract:

Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by a power supply voltage generator circuit, the generated power supply voltage being substantially equal to or less than a global power supply voltage provided to one or more transistors of the SRAM cell during a write-enable or power-down mode.

US Patent:

7639057, Dec 29, 2009

Filed:

Dec 3, 2007

Appl. No.:

11/949424

Inventors:

Jason T. Su - Los Altos CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 1/04
H03K 3/00

US Classification:

327291, 326 93, 326 96, 326 97

Abstract:

A clock gater includes a first logic circuit that receives an enable signal and that includes first and second subcircuits. The clock gater also includes a latch that shares first and second nodes with the first logic circuit and that includes third and fourth subcircuits. The first logic circuit and the latch receive a clock signal that varies between first and second clock states. The first and third subcircuits pull the first and second nodes, respectively, to a common precharge voltage based on the first clock state in order to pass the clock signal. The second and fourth subcircuits pull the first and second nodes, respectively, to complementary voltages based on the second clock state to pass the clock signal. The first node passes the clock signal or gates the clock signal based on the enable signal.

US Patent:

7777550, Aug 17, 2010

Filed:

Feb 24, 2009

Appl. No.:

12/392021

Inventors:

Jason Su - Los Altos CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03L 5/00

US Classification:

327333, 326 63, 326 81

Abstract:

A circuit receives an input signal characterized by a first pair of rail voltages and generates in response thereto an output signal characterized by a second pair of rail voltages. The circuit comprises first and second transistors coupled in series between a high reference voltage and a low reference voltage. The input signal drives a control lead of the second transistor. The logical inverse of the input signal drives a control lead of a third transistor, which couples a charge source to the control lead of the first transistor in response thereto in order to turn off the first transistor. The charge source can be either a voltage source or a charged capacitive node. Of importance, the third transistor does not have to overcome contention with other transistors to turn off said first transistor.

US Patent:

7787324, Aug 31, 2010

Filed:

Oct 11, 2007

Appl. No.:

11/870833

Inventors:

Sehat Sutardja - Los Altos Hills CA, US
Jason T. Su - Los Altos CA, US
Hong-Yi Chen - Fremont CA, US
Jason Sheu - Cupertino CA, US
Jensen Tjeng - San Jose CA, US

Assignee:

Marvell World Trade Ltd. - St. Michael

International Classification:

G11C 8/00

US Classification:

36523006, 365154, 365202, 365203

Abstract:

A processor includes a cache memory. The cache memory includes an array of cells, word lines and bit lines. A control module enables a word line of the word lines to access a first cell in the enabled word line. The control module disables the word line and maintains the word line in a disabled state to access a second cell in the word line.

US Patent:

7835217, Nov 16, 2010

Filed:

Aug 25, 2009

Appl. No.:

12/547182

Inventors:

Jason T. Su - Los Altos CA, US
Karthik Swaminathan - San Jose CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G11C 5/14

US Classification:

365226, 365154

Abstract:

Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by a power supply voltage generator circuit, the generated power supply voltage being substantially equal to or less than a global power supply voltage provided to one or more transistors of the SRAM cell during a write-enable or power-down mode.

US Patent:

7848173, Dec 7, 2010

Filed:

Oct 17, 2007

Appl. No.:

11/873505

Inventors:

Jason T. Su - Los Altos CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G11C 8/00

US Classification:

36523006, 36518908, 365233

Abstract:

An address decoder includes N predecoders that receive and logically combine a clock signal and respective address signals to periodically provide respective addresses and complementary addresses. N is an integer greater than one. A first decoder receives the respective addresses and complementary addresses and generates a decoder output based on the received respective addresses and complementary addresses.

US Patent:

7855587, Dec 21, 2010

Filed:

May 30, 2007

Appl. No.:

11/755564

Inventors:

Jason Su - Los Altos CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03K 3/00

US Classification:

327218, 327208

Abstract:

An Asymmetric Sense-Amp Flip-Flop (ASAFF) is disclosed that may achieve zero setup time and short clock-to-Q delays. The ASAFF captures input data at a clock transition by setting values of a first node and a second node in a manner that is input data value dependent. If the input data is at the first input data value, the first node is set and held at a first storage value after a first delay, and the second node is set and held at a second storage value after a second delay, and if the input data is at a second input data value, the first node is set and held at a third storage value after a third delay, and the second node is set and held at a fourth storage value, after a fourth delay. This internal-path dependent difference in delay enables ASAFF to achieve zero setup time.

US Patent:

7965123, Jun 21, 2011

Filed:

Jul 6, 2010

Appl. No.:

12/831091

Inventors:

Jason Su - Los Altos CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03L 5/00

US Classification:

327333, 326 63, 326 81

Abstract:

A circuit receives an input signal characterized by a first pair of rail voltages and generates in response thereto an output signal characterized by a second pair of rail voltages. The circuit comprises first and second transistors coupled in series between a high reference voltage and a low reference voltage. The input signal drives a control lead of the second transistor. The logical inverse of the input signal drives a control lead of a third transistor, which couples a charge source to the control lead of the first transistor in response thereto in order to turn off the first transistor. The charge source can be either a voltage source or a charged capacitive node. Of importance, the third transistor does not have to overcome contention with other transistors to turn off said first transistor.