Jay T Schwartz

US Patent:

8611170, Dec 17, 2013

Filed:

Dec 30, 2011

Appl. No.:

13/341868

Inventors:

Timothy Y. Kam - Portland OR, US
Jay D. Schwartz - Aloha OR, US
Seongwoo Kim - Beaverton OR, US
Stephen H. Gunther - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 5/14

US Classification:

365226, 365102, 365 94, 365149, 365150, 36518917, 365191, 365227, 36523006, 36523313

Abstract:

Power management of an embedded dynamic random access memory (eDRAM) using collected performance counter statistics to generating a set of one or more eDRAM effectiveness predictions. Using a set of one or more eDRAM effectiveness thresholds, each corresponding to one of the set of eDRAM effectiveness predictions, to determine whether at least one eDRAM effectiveness prediction has crossed over threshold. In the case that at least one eDRAM effectiveness prediction has crossed over its threshold, transitioning the eDRAM to a new power state. Power management is achieved by transitioning to a power-off state or self-refresh state and reducing the amount of power consumed by the eDRAM as compared to a power-on state.

US Patent:

20120166822, Jun 28, 2012

Filed:

Dec 30, 2011

Appl. No.:

13/341864

Inventors:

TIMOTHY Y. KAM - Portland OR, US
JAY D. SCHWARTZ - Aloha OR, US
SEONGWOO KIM - Beaverton OR, US
STEPHEN H. GUNTHER - Beaverton OR, US

International Classification:

G06F 1/26

US Classification:

713300

Abstract:

Power management of an embedded dynamic random access memory (eDRAM) by receiving an eDRAM power state transition event and determining both the current power state of the eDRAM and the next power state of the eDRAM from the power states of: a power-on state, a power-off state, and a self-refresh state. Using the current power state and the next power state to determine whether a power state transition is required, and, in the case that a power state transition is required, transition the eDRAM to the next power state. Power management is achieved because transitioning to a power-off state or self-refresh state reduces the amount of power consumed by the eDRAM as compared to the power-on state.

US Patent:

20120173895, Jul 5, 2012

Filed:

Dec 5, 2011

Appl. No.:

13/311467

Inventors:

Seongwoo Kim - Beaverton OR, US
Jeremy Shrall - Portland OR, US
Jay D. Schwartz - Aloha OR, US
Stephen H. Gunther - Beaverton OR, US
Travis C. Furrer - Hillsboro OR, US

International Classification:

G06F 1/00

US Classification:

713300

Abstract:

The efficiency rating (ER) of each domain, in a processor, may be compared and then the power budget may be allocated, effectively, among the domains based on the ERs of the domains. The ER may indicate relative advantage among domains in terms of performance return for a given power budget, i.e., a higher effectiveness may be expected in power utilization if the ER is higher for a domain. The ER of a domain may be defined as (scalability factor/cost factor*alpha). The scalability factor may be defined as a performance increase (in %) brought about by an increase in the clock frequency (in %) provided to the domain. The cost factor may be defined as a power budget value required in bringing about an increase in the clock frequency provided to the domain and alpha is an adjustment factor.

US Patent:

20140068291, Mar 6, 2014

Filed:

Aug 31, 2012

Appl. No.:

13/600666

Inventors:

XIUTING C. MAN - Portland OR, US
MICHAEL N. DERR - El Dorado Hills CA, US
JAY D. SCHWARTZ - Aloha OR, US
STEPHEN H. GUNTHER - Beaverton OR, US
JEREMY J. SHRALL - Portland OR, US
SHAUN M. CONRAD - Cornelius OR, US
AVINASH N. ANANTHAKRISHAN - Hillsboro OR, US

International Classification:

G06F 1/26
G06F 1/32

US Classification:

713320

Abstract:

In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.

US Patent:

20140068293, Mar 6, 2014

Filed:

Mar 4, 2013

Appl. No.:

13/783978

Inventors:

Xiuting C. Man - Portland OR, US
Michael N. Derr - El Dorado Hills CA, US
Jay D. Schwartz - Aloha OR, US
Stephen H. Gunther - Beaverton OR, US
Jeremy J. Shrall - Portland OR, US
Shaun M. Conrad - Cornelius OR, US
Avinash N. Ananthakrishnan - Hillsboro OR, US

International Classification:

G06F 1/32

US Classification:

713320

Abstract:

In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.

US Patent:

20170147054, May 25, 2017

Filed:

Feb 7, 2017

Appl. No.:

15/426876

Inventors:

- Santa Clara CA, US
ELIEZER WEISSMANN - Haifa, IL
EFRAIM ROTEM - Haifa, IL
PAUL S. DIEFENBAUGH - Portland OR, US
JAY D. SCHWARTZ - Aloha OR, US
SHARAD C. TRIPATHI - Portland OR, US

International Classification:

G06F 1/32

Abstract:

Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.

US Patent:

20150370304, Dec 24, 2015

Filed:

Jun 24, 2014

Appl. No.:

14/313597

Inventors:

HISHAM ABU SALAH - Majdal Shams, IL
ELIEZER WEISSMANN - Haifa, IL
EFRAIM ROTEM - Haifa, IL
PAUL S. DIEFENBAUGH - Portland OR, US
JAY D. SCHWARTZ - Aloha OR, US
SHARAD C. TRIPATHI - Portland OR, US

International Classification:

G06F 1/32

Abstract:

Techniques described above may enhance the power-performance efficiency of a processor, SoC, or a computing system. Embodiments described here allow an increase in frequency of the clock signal to a peak frequency value in response to detecting an occurrence of a burst of high activity within the low processor utilization periods. A power management unit may accumulate the budget during the low or idle processor utilization periods and the level of activity of the burst of high activity signal may be determined. The PMU may increase the frequency of the clock signal provided to the processing cores if the level of the burst of high activity exceeds a first threshold value and an accumulated budget value exceeds a second threshold value.

US Patent:

20150241954, Aug 27, 2015

Filed:

Apr 27, 2015

Appl. No.:

14/697553

Inventors:

Avinash N. Ananthakrishnan - Portland OR, US
Julien Sebot - Portland OR, US
Jay D. Schwartz - Aloha OR, US
Stephen H. Gunther - Beaverton OR, US
Eric C. Samson - Folsom CA, US

International Classification:

G06F 1/32

Abstract:

A processor is described that includes a plurality of execution units in a processor core. The processor also may include power management circuitry to determine a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units for a same active performance state. A method may include determining with power management circuitry of a processor a configuration with a lowest power cost from a plurality of configurations that each have a different number of enabled execution units in a processor core of the processor for a same active performance state.