Jay Young

US Patent:

6944809, Sep 13, 2005

Filed:

Aug 6, 2002

Appl. No.:

10/214025

Inventors:

Andrew W. Lai - Fremont CA, US
Randy J. Simmons - San Jose CA, US
Teymour M. Mansour - Sunnyvale CA, US
Vincent L. Tong - Fremont CA, US
Jeffrey V. Lindholm - Longmont CO, US
Jay T. Young - Louisville CO, US
William R. Troxel - Longmont CO, US
Sridhar Krishnamurthy - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G01R031/28

US Classification:

714725, 714724

Abstract:

Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.

Address:

1229 Diamond Cv Pl, El Paso, TX 79912

VIN:

JM1BK143271676323

Make:

MAZDA

Model:

MAZDA3

Year:

2007