Jayasimha S Prasad

US Patent:

6699765, Mar 2, 2004

Filed:

Aug 29, 2002

Appl. No.:

10/231986

Inventors:

Jay Albert Shideler - Los Altos Hills CA
Jayasimha Swamy Prasad - San Jose CA
Ronald Lloyd Schlupp - Los Gatos CA
Robert William Bechdolt - San Jose CA

Assignee:

Micrel, Inc. - San Jose CA

International Classification:

H01L 218222

US Classification:

438312, 438350, 438365, 438481

Abstract:

Embodiments of a bipolar transistor are disclosed, along with methods for making the transistor. An exemplary transistor includes a collector region in a semiconductor substrate, a base layer overlying the collector region and bound by a field oxide layer, a dielectric isolation layer overlying the base layer, and an emitter structure overlying the dielectric isolation layer and contacting the base layer through a central aperture in the dielectric layer. The transistor may be a heterojunction bipolar transistor with the base layer formed of a selectively grown silicon germanium alloy. A dielectric spacer may be formed adjacent the emitter structure and over a portion of the base layer.

US Patent:

6913981, Jul 5, 2005

Filed:

May 19, 2003

Appl. No.:

10/441763

Inventors:

Jay Albert Shideler - Los Altos Hills CA, US
Jayasimha Swamy Prasad - San Jose CA, US
Ronald Lloyd Schlupp - Los Gatos CA, US
Robert William Bechdolt - San Jose CA, US

Assignee:

Micrel, Incorporated - San Jose CA

International Classification:

H01L021/8222

US Classification:

438309, 438312, 438365

Abstract:

Embodiments of a bipolar transistor are disclosed, along with methods for making the transistor. An exemplary transistor includes a collector region in a semiconductor substrate, a base layer overlying the collector region and bound by a field oxide layer, a dielectric isolation layer overlying the base layer, and an emitter structure overlying the dielectric isolation layer and contacting the base layer through a central aperture in the dielectric layer. The transistor may be a heterojunction bipolar transistor with the base layer formed of a selectively grown silicon germanium alloy. A dielectric spacer may be formed adjacent the emitter structure and over a portion of the base layer.

US Patent:

8647950, Feb 11, 2014

Filed:

Aug 10, 2012

Appl. No.:

13/572428

Inventors:

Marco A. Zuniga - Palo Alto CA, US
Yang Lu - Fremont CA, US
Badredin Fatemizadeh - Sunnyvale CA, US
Jayasimha Prasad - San Jose CA, US
Amit Paul - Sunnyvale CA, US
Jun Ruan - Santa Clara CA, US

Assignee:

Volterra Semiconductor Corporation - Fremont CA

International Classification:

H01L 21/336

US Classification:

438270, 438286, 438589, 257E21621

Abstract:

A method of fabricating a vertical gate region in LDMOS transistor includes depositing a first masking layer on an n-well region implanted on a substrate, patterning the first masking layer to define an area, depositing a second masking layer over the area, etching through the second masking layer in a first portion of the area to expose the n-well region, and etching the exposed n-well region to form a first trench. The first trench, extending from a surface of the n-well region to a first depth, is filled with an oxide. The second masking layer is etched through in a second portion of the area to expose the n-well region. A second trench is formed in the n-well, the second trench extending from the surface to a second depth, less than the first depth. An asymmetric vertical gate is formed by filling the second trench with a conductive material.

US Patent:

20130105887, May 2, 2013

Filed:

Aug 10, 2012

Appl. No.:

13/572015

Inventors:

Marco A. Zuniga - Palo Alto CA, US
Yang Lu - Fremont CA, US
Badredin Fatemizadeh - Sunnyvale CA, US
Jayasimha Prasad - San Jose CA, US
Amit Paul - Sunnyvale CA, US
Jun Ruan - Santa Clara CA, US

Assignee:

Volterra Semiconductor Corporation - Fremont CA

International Classification:

H01L 29/78
H01L 29/66

US Classification:

257330, 438270

Abstract:

Described here are transistors and fabrication methods thereof. In one implementation, a transistor includes an n-well region implanted into a surface of a substrate, and a trench in the n-well region. The trench extends from the surface to a first depth. The trench includes a gate of conductive material in the trench, and dielectric material filling a volume of the trench not filled by the conductive material. The transistor also includes a p-type material in a first region extending from a second depth to a third depth, the second depth and the third depth being greater than the first depth. The transistor further includes a source region and a drain region.

US Patent:

20130105888, May 2, 2013

Filed:

Aug 10, 2012

Appl. No.:

13/572110

Inventors:

Marco A. Zuniga - Palo Alto CA, US
Yang Lu - Fremont CA, US
Badredin Fatemizadeh - Sunnyvale CA, US
Jayasimha Prasad - San Jose CA, US
Amit Paul - Sunnyvale CA, US
Jun Ruan - Santa Clara CA, US

Assignee:

Volterra Semiconductor Corporation - Fremont CA

International Classification:

H01L 29/78

US Classification:

257330, 257335

Abstract:

The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.

US Patent:

20130109143, May 2, 2013

Filed:

Aug 10, 2012

Appl. No.:

13/572281

Inventors:

Marco A. Zuniga - Palo Alto CA, US
Yang Lu - Fremont CA, US
Badredin Fatemizadeh - Sunnyvale CA, US
Jayasimha Prasad - San Jose CA, US
Amit Paul - Sunnyvale CA, US
Jun Ruan - Santa Clara CA, US
John Xia - Fremont CA, US

Assignee:

Volterra Semiconductor Corporation - Fremont CA

International Classification:

H01L 29/78

US Classification:

438270

Abstract:

The present application features methods of fabricating a gate region in a vertical laterally diffused metal oxide semiconductor (LDMOS) transistor. In one aspect, a method includes depositing a masking layer on an n-well region implanted on a substrate, patterning the masking layer to define an area, and forming a first trench in the area such that a length of the first trench extends from a surface of the n-well region to a first depth in the n-well region. The method also includes filling the first trench by a conductive material and depositing a layer of oxide over the area. The method further includes etching out at least a portion of the oxide layer to expose a portion of the conductive material, removing the conductive material from the exposed portion to form a second trench, and filling the second trench with an oxide to form an asymmetric gate of the transistor.

US Patent:

52683150, Dec 7, 1993

Filed:

Sep 4, 1992

Appl. No.:

7/940588

Inventors:

Jayasimha S. Prasad - Tigard OR
Song W. Park - Aloha OR
William A. Vetanen - Sherwood OR
Irene G. Beers - Sherwood OR
Curtis M. Haynes - Portland OR

Assignee:

Tektronix, Inc. - Wilsonville OR

International Classification:

H01L 21265

US Classification:

437 31

Abstract:

The disclosed HBT IC process can fabricate npn heterojunction bipolar transistors, Schottky diodes, MIM capacitors, spiral inductors, and NiCr resistors. Two levels of interconnect metal are available. The first level metal is a conventional dielectric-insulated metal conductor. The second level metal includes an air-bridge for contacting the HBT emitters, which are on top of three level mesa structures. It is also an advanced low loss, low capacitance, air dielectric conductor useful for long interconnects and inductors. MIM capacitors are formed by sandwiching silicon nitride between the first layer metal and a capacitor top plate made with landed air-bridge metal. Precision thin film resistors are fabricated by depositing NiCr on silicon nitride. The three-level active mesa structure is etched down to the GaAs substrate, for lateral device isolation, with a truncated pyramidal shape which permits good step coverage of dielectric and metallization layers. The wet etching process uses a composition of H. sub. 3 PO. sub. 4 :H. sub. 2 O. sub. 2 :H. sub.

US Patent:

63296985, Dec 11, 2001

Filed:

Sep 21, 1999

Appl. No.:

9/399911

Inventors:

Waclaw C. Koscielniak - Santa Clara CA
Kulwant S. Egan - San Jose CA
Jayasimha S. Prasad - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H01K 27082

US Classification:

257565

Abstract:

An improved method and an apparatus for forming a self-aligned epitaxial base bipolar transistor in a semiconductor material is disclosed. The method of the invention involves forming an intrinsic base region formed by growing an epitaxial semiconductor material over a collector region. A raised sacrificial emitter core is then formed on the intrinsic base region followed by depositing a substantially conformal spacer layer over the sacrificial emitter core. Next, the spacer material is anisotropically etched such that a protective spacer ring is formed about the sacrificial emitter core. An extrinsic base is then formed by implanting dopant into the epitaxial base region wherein the sacrificial emitter core and the spacer ring preserve an emitter region. The spacer ring also serves to self-align the extrinsic base region to the emitter region. The protective sacrificial emitter core and spacer ring are then removed.