Jayesh N Patel

US Patent:

6393390, May 21, 2002

Filed:

Dec 6, 1999

Appl. No.:

09/455063

Inventors:

Jayesh S. Patel - Lowell MA 01851
Douglas E. Kolb - Bedford MA 01730

International Classification:

G10L 1904

US Classification:

704207, 704219, 704220, 704222, 704223

Abstract:

A method and apparatus for reducing the complexity of linear prediction analysis-by-synthesis (LPAS) speech coders. The method and apparatus include product code vector quantization (PCVQ) of multi-tap pitch predictor coefficients, which reduces the search and quantization complexity of an adaptive codebook. The pitch predictor vector quantizes the predictor parameters using at least two codebooks, which are effectively subcodebooks of the pitch predictor adaptive codebook. Further included is a procedure for generating and selecting code vectors consisting of ternary (1,0,-1) values, for optimizing a fixed codebook. The fixed codebook makes a single pass derivation of pulse position in the excitation signal. Serial optimization of the adaptive codebook first and then the fixed codebook, produces a low complexity LPAS speech coder of the present invention.

US Patent:

6865530, Mar 8, 2005

Filed:

Nov 21, 2001

Appl. No.:

09/991763

Inventors:

Jayesh S. Patel - Lowell MA, US
Douglas E. Kolb - Bedford MA, US

International Classification:

G10L019/10
G10L019/12

US Classification:

704223, 704220, 704222

Abstract:

A method and apparatus for reducing the complexity of linear prediction analysis-by-synthesis (LPAS) speech coders. The speech coder includes a multi-tap pitch predictor having various parameters and utilizing an adaptive codebook subdivided into at least a first vector codebook and a second vector codebook. The pitch predictor removes certain redundancies in a subject speech signal and vector quantizes the pitch predictor parameters. Further included is a source excitation (fixed) codebook that indicates pulses in the subject speech signal by deriving corresponding vector values. Serial optimization of the adaptive codebook first and then the fixed codebook produces a low complexity LPAS speech coder of the present invention.

US Patent:

7200553, Apr 3, 2007

Filed:

Jan 24, 2005

Appl. No.:

11/041478

Inventors:

Jayesh S. Patel - Lowell MA, US
Douglas E. Kolb - Bedford MA, US

Assignee:

Tellabs Operations, Inc. - Naperville IL

International Classification:

G10L 19/08

US Classification:

704223

Abstract:

A method and apparatus for reducing the complexity of linear prediction analysis-by-synthesis (LPAS) speech coders. The speech coder includes a multi-tap pitch predictor having various parameters and utilizing an adaptive codebook subdivided into at least a first vector codebook and a second vector codebook. The pitch predictor removes certain redundancies in a subject speech signal and vector quantizes the pitch predictor parameters. Further included is a source excitation (fixed) codebook that indicates pulses in the subject speech signal by deriving corresponding vector values. Serial optimization of the adaptive codebook first and then the fixed codebook produces a low complexity LPAS speech coder of the present invention.

US Patent:

7359855, Apr 15, 2008

Filed:

Jan 12, 2007

Appl. No.:

11/652732

Inventors:

Jayesh S. Patel - Lowell MA, US
Douglas E. Kolb - Bedford MA, US

Assignee:

Tellabs Operations, Inc. - Naperville IL

International Classification:

G10L 19/10

US Classification:

704223, 704220, 704222

Abstract:

A method and apparatus for reducing the complexity of linear prediction analysis-by synthesis (LPAS) speech coders. The speech coder includes a multi-tap pitch predictor having various parameters and utilizing an adaptive codebook subdivided into at least a first vector codebook and a second vector codebook. The pitch predictor removes certain redundancies in a subject speech signal and vector quantizes the pitch predictor parameters.

US Patent:

8521457, Aug 27, 2013

Filed:

Oct 20, 2008

Appl. No.:

12/254290

Inventors:

Jayesh Patel - Salisbury MA, US
Michael Drummy - North Reading MA, US

Assignee:

Olympus NDT - Waltham MA

International Classification:

G01R 19/00
G01N 11/00
G01N 27/82
G01N 29/06
G01N 27/90

US Classification:

702 64, 702 56, 702 54, 702 59, 702 67, 702171

Abstract:

A user configured measurement display system and method for a non-destructive testing device and instrument (NDT/NDI) with high input data rate is disclosed. The system and the method provide the means for NDT/NDI instruments display measurement values that satisfies user designated measurement criterion occurring during any measurement time intervals (MTIs). The present disclosure overcomes the shortcomings of conventional ways of picking and displaying measurement values at fixed MTIs, by which the values truly satisfying the measurement criterion that occurs at random MTIs (other than scheduled MTIs) are often skipped.

US Patent:

8554968, Oct 8, 2013

Filed:

Mar 21, 2011

Appl. No.:

13/052388

Inventors:

Peter Z. Onufryk - Flanders NJ, US
Jayesh Patel - San Jose CA, US
Ihab Jaser - San Jose CA, US

Assignee:

PMC-Sierra, Inc. - Sunnyvale CA

International Classification:

G06F 13/24

US Classification:

710260, 710 48, 710269

Abstract:

A nonvolatile memory controller processes a nonvolatile memory command and generates a completion status for the nonvolatile memory command. The nonvolatile memory controller transmits the completion status to a host processing unit for storage in a completion queue of the host processing unit. An interrupt manager in the nonvolatile memory controller determines the completion queue contains an unprocessed completion status and generates an interrupt message packet. The nonvolatile memory controller transmits the interrupt message packet to the host processing unit for triggering an interrupt in the host processing unit and alerting the host processing unit to the unprocessed completion status.

US Patent:

8588228, Nov 19, 2013

Filed:

Mar 18, 2011

Appl. No.:

13/052008

Inventors:

Peter Z. Onufryk - Flanders NJ, US
Jayesh Patel - San Jose CA, US
Ihab Jaser - San Jose CA, US
Ganesh T. Seshan - Fremont CA, US

Assignee:

PMC-Sierra US, Inc. - Sunnyvale CA

International Classification:

H04L 12/28

US Classification:

370389, 710316

Abstract:

A nonvolatile memory controller includes a host controller interface, processors, a message networks and a data network. The host controller interface includes a command fetch module, command assembly buffers, and a command dispatch module. The command fetch module retrieves nonvolatile memory commands from a host processing unit. The command assembly buffers store the nonvolatile memory commands retrieved from the host processing unit. The command dispatch module generates request message packets including the nonvolatile memory commands. The message network routes the request message packets to the processors. The processors process the nonvolatile memory commands in the request message packets for controlling operation of the nonvolatile memory controller.

US Patent:

8595158, Nov 26, 2013

Filed:

Jun 10, 2011

Appl. No.:

13/157833

Inventors:

Jayesh Patel - Tyngsboro MA, US
John C. Apostle - Lowell MA, US
Richard K. Seiffert - Wilmington MA, US

Assignee:

Triasys Technologies Corporation - Billerica MA

International Classification:

G06F 15/18

US Classification:

706 12, 370255

Abstract:

A system and method for associating Signaling System 7 logical circuits and bearer channels are presented. The system may include an event detector configured to receive an SS7 signaling message on an SS7 signaling link, parse a logical circuit from the SS7 signaling message, receive an SS7 bearer channel, and detect a bearer channel event on the SS7 bearer channel. A statistical learning model block is configured to calculate a correlation confidence value between said bearer channel and said logical circuit. The method may include parsing a logical circuit ID from a signaling message on an SS7 signal link, identifying a bearer channel associated with a bearer event on a bearer circuit, and calculating a current correlation confidence value between the logical circuit ID and the bearer channel.