Jayson S Preece

US Patent:

20120267711, Oct 25, 2012

Filed:

Apr 21, 2011

Appl. No.:

13/091681

Inventors:

Thomas E. Grebs - South Jordan UT, US
Jayson S. Preece - Riverton UT, US

International Classification:

H01L 29/78

US Classification:

257331, 257E29262, 257E29264

Abstract:

This document discusses, among other things, a semiconductor device including first and second conductive layers, the first conductive layer including a gate runner and a drain contact and the second conductive layer including a drain conductor, at least a portion of the drain conductor overlying at least a portion of the gate runner. A first surface of the semiconductor device can include a gate pad coupled to the gate runner and a drain pad coupled to the drain contact and the drain conductor.

US Patent:

20140264569, Sep 18, 2014

Filed:

Mar 11, 2014

Appl. No.:

14/204765

Inventors:

- San Jose CA, US
Dean E. PROBST - West Jordan UT, US
Richard STOKES - Shavertown PA, US
Suku KIM - South Jordan UT, US
Jason HIGGS - Mountain Top PA, US
Fred SESSION - Sandy UT, US
Hui CHEN - South Jordan UT, US
Steven P. SAPP - Felton CA, US
Jayson PREECE - Riverton UT, US
Mark L. Rinehimer - Mountain Top PA, US

Assignee:

Fairchild Semiconductor Corporation - San Jose CA

International Classification:

H01L 29/78
H01L 21/02
H01L 29/06

US Classification:

257330, 257618, 438478

Abstract:

In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region.