Jeanne M Mcnamara

US Patent:

6365953, Apr 2, 2002

Filed:

Apr 1, 1999

Appl. No.:

09/283530

Inventors:

Patrick Anthony Begley - West Melbourne FL
Donald Frank Hemmenway - Melbourne FL
George Bajor - Melbourne FL
Anthony Lee Rivoli - Palm Bay FL
Jeanne Marie McNamara - Palm Bay FL
Michael Sean Carmody - Palm Bay FL
Dustin Alexander Woodbury - Indian Harbour Beach FL

Assignee:

Intersil Americas Inc. - Irvine CA

International Classification:

H01L 2900

US Classification:

257513, 257506, 257510, 257520

Abstract:

A bonded wafer has a device substrate with isolation trenches defining device regions Oxide dogbone structures are removed before filling trenches Voids in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer and filled with polysilicon A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride cover the trenches and the adjacent device substrate regions.

US Patent:

6551897, Apr 22, 2003

Filed:

Nov 16, 2001

Appl. No.:

09/993968

Inventors:

Patrick Anthony Begley - West Melbourne FL
Donald Frank Hemmenway - Melbourne FL
George Bajor - Melbourne FL
Anthony Lee Rivoli - Palm Bay FL
Jeanne Marie McNamara - Palm Bay FL
Michael Sean Carmody - Palm Bay FL
Dustin Alexander Woodbury - Indian Harbour Beach FL

Assignee:

Intersil Americas Inc. - Irvine CA

International Classification:

H01L 21762

US Classification:

438404, 438406, 438437

Abstract:

A bonded wafer has a device substrate with isolation trenches defining device regions Oxide dogbone structures are removed before filling trenches. Voids in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer and filled with polysilicon A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride cover the trenches and the adjacent device substrate regions.

US Patent:

59337460, Aug 3, 1999

Filed:

Apr 23, 1996

Appl. No.:

8/637937

Inventors:

Patrick Anthony Begley - West Melbourne FL
Donald Frank Hemmenway - Melbourne FL
George Bajor - Melbourne FL
Anthony Lee Rivoli - Palm Bay FL
Jeanne Marie McNamara - Palm Bay FL
Michael Sean Carmody - Palm Bay FL
Dustin Alexander Woodbury - Indian Harbour Beach FL

Assignee:

Harris Corporation - Palm Bay FL

International Classification:

H01L 2176

US Classification:

438405

Abstract:

A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.

US Patent:

55166253, May 14, 1996

Filed:

Sep 8, 1993

Appl. No.:

8/118063

Inventors:

Jeanne M. McNamara - Palm Bay FL
Deborah K. Rodriguez - Palm Bay FL
David H. Leebrick - Palm Bay FL

Assignee:

Harris Corporation - Melbourne FL

International Classification:

G03F 726

US Classification:

430314

Abstract:

To planarize an oxide-filled shallow trench-isolated semiconductor architecture, a composite photoresist sacrificial layer is initially formed on the oxide-filled structure. The composite photoresist layer contains photoresist plugs which are reflowed to fill depressions in the oxide fill layer overlying the trench, and an overlying photoresist layer which effectively planarizes the depression-filled trench oxide layer. Respective photoresist and oxide selective etching chemistries are then successively applied to first etch the composite sacrificial photoresist layer and then etch the trench fill oxide layer down to the surface of an etch stop polysilicon layer. Since the thickness of the polysilicon etch stop layer is initially formed so as to extend above the mesa layer of the trench-isolated semiconductor structure by a relatively nominal height, after planarization, the top surface of the trench fill oxide layer still extends above the surface of the mesa to prevent shorting of a subsequently formed polysilicon gate layer with underlying mesa material, while being sufficiently low enough to avoid sidewall stringer formation.

US Patent:

56486782, Jul 15, 1997

Filed:

Sep 21, 1994

Appl. No.:

8/310280

Inventors:

Patrick A. Begley - W. Melbourne FL
John T. Gasner - Palm Bay FL
Lawrence G. Pearce - Palm Bay FL
Choong S. Rhee - Palm Bay FL
Jeanne M. McNamara - Palm Bay FL
John J. Hackenberg - Palm Bay FL
Donald F. Hemmenway - Melbourne FL

Assignee:

Harris Corporation - Melbourne FL

International Classification:

H01L 2900

US Classification:

257529

Abstract:

An integrated circuit 10 has a programmable Zener diode with diffusion regions 18 and 16 and metal contacts 34 and 32. A barrier metal 30 is disposed between one contact 32 and the substrate 12; another contact region 18 has no barrier metal on its surface. A polysilicon layer 22 is self-aligned with surface regions 18 and diffusion region 18. A silicide layer 128 may be used on the polysilicon layer 22 and on surface region 18.