Jed Jerome Krohnfeldt

age ~70

from Estero, FL

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Also known as:
  • Jed J Krohnfeldt
  • Jed J Krohnfel
  • Jed J Krohnfeld
  • Jed T
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Jed Krohnfeldt Phones & Addresses

  • Estero, FL
  • Salt Lake City, UT
  • 232 Bacigalupi Dr, Los Gatos, CA 95032 • 4083562807
  • Cupertino, CA
  • Milpitas, CA
  • Santa Clara, CA
  • Fremont, CA
  • San Jose, CA
  • 232 Bacigalupi Dr, Los Gatos, CA 95032

Work

  • Company:
    Cumulus systems
    Feb 2013
  • Position:
    Vice president of engineering

Education

  • Degree:
    Associate degree or higher

Skills

Software Engineering • Enterprise Software • Integration • C++ • Device Drivers • Digital Signal Processors • Storage • Distributed Systems • Management • Perl • Nas • Start Ups • Virtualization • Cloud Computing • Semiconductors • Asic • Soc • Enterprise Storage • Analysis • Ic • Tcl • C • Telecommunications • Eda • Technical Leadership

Industries

Computer Software

Resumes

Jed Krohnfeldt Photo 1

Vice President Of Engineering

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Location:
232 Bacigalupi Dr, Los Gatos, CA 95032
Industry:
Computer Software
Work:
Cumulus Systems
Vice President of Engineering
Montana Systems Apr 2011 - Jan 2013
Director of Sw
Ikoa Corporation Mar 2005 - Dec 2010
Director of Sw Engineering
Hitachi Data Systems Mar 2005 - Mar 2006
Senior Director of Sw Engineering
Hitachi Storage Software Sep 2001 - Mar 2005
Vice President of Engineering
Skills:
Software Engineering
Enterprise Software
Integration
C++
Device Drivers
Digital Signal Processors
Storage
Distributed Systems
Management
Perl
Nas
Start Ups
Virtualization
Cloud Computing
Semiconductors
Asic
Soc
Enterprise Storage
Analysis
Ic
Tcl
C
Telecommunications
Eda
Technical Leadership
Name / Title
Company / Classification
Phones & Addresses
Jed Krohnfeldt
Manager
HITACHI STORAGE SOFTWARE INCORPORATED
Other Electronic Component Manufacturing
3031 Tisch Way SUITE 200, San Jose, CA 95128
4085536610

Us Patents

  • Method For Specifying Stateful, Transaction-Oriented Systems For Flexible Mapping To Structurally Configurable, In-Memory Processing Semiconductor Device

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  • US Patent:
    20070150854, Jun 28, 2007
  • Filed:
    Jun 27, 2006
  • Appl. No.:
    11/426882
  • Inventors:
    Shridhar Mukund - San Jose CA, US
    Anjan Mitra - Santa Clara CA, US
    Jed Krohnfeldt - Los Gatos CA, US
    Clement Leung - Fremont CA, US
  • International Classification:
    G06F 9/44
  • US Classification:
    717104000
  • Abstract:
    A method for specifying stateful, transaction-oriented systems is provided. The method initiates with designating a plurality of primitive FlowModules. The method includes defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptible sequence of procedure code, a single point of entry and is invoked by a named concurrent call. An Arc is designated from a calling FlowGate to a called FlowGate and a Signal is generated for each named invocation of the called FlowGate. A Channel is defined for carrying the Signal. Methods for synthesizing a semiconductor device and routing signals in the semiconductor device are provided.

  • Method For Specifying Stateful, Transaction-Oriented Systems For Flexible Mapping To Structurally Configurable In-Memory Processing Semiconductor Device

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  • US Patent:
    20110035722, Feb 10, 2011
  • Filed:
    Oct 18, 2010
  • Appl. No.:
    12/906967
  • Inventors:
    Shridhar Mukund - San Jose CA, US
    Anjan Mitra - Santa Clara CA, US
    Jed Krohnfeldt - Los Gatos CA, US
    Clement Leung - Fremont CA, US
  • International Classification:
    G06F 9/44
  • US Classification:
    717104
  • Abstract:
    A method for specifying stateful, transaction-oriented systems is provided. The method initiates with designating a plurality of primitive FlowModules. The method includes defining at least one FlowGate within each of the plurality of FlowModules, wherein each FlowGate includes a non-interruptible sequence of procedure code, a single point of entry and is invoked by a named concurrent call. An Arc is designated from a calling FlowGate to a called FlowGate and a Signal is generated for each named invocation of the called FlowGate. A Channel is defined for carrying the Signal. Methods for synthesizing a semiconductor device and routing signals in the semiconductor device are provided.
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