Jeffrey A Cooper

US Patent:

20210111861, Apr 15, 2021

Filed:

Dec 21, 2020

Appl. No.:

17/128720

Inventors:

- Santa Clara CA, US
- Markham, CA
Gerald R. Talbot - Boxborough MA, US
Gurunath Dollin - Santa Clara CA, US
Damon Tohidi - Markham, CA
Eric Ian Carpenter - Fort Collins CO, US
Chad S. Gallun - Austin TX, US
Jeffrey Cooper - Fort Collins CO, US
Hanwoo Cho - Santa Clara CA, US
Scott F. Dow - Fruita CO, US
Michael J. Tresidder - Austin TX, US

International Classification:

H04L 7/04
H04L 7/00

Abstract:

Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

US Patent:

20210090615, Mar 25, 2021

Filed:

Dec 7, 2020

Appl. No.:

17/113346

Inventors:

- Santa Clara CA, US
Jeffrey Cooper - Ft. Collins CO, US

International Classification:

G11C 7/06
G11C 15/04

Abstract:

Systems, apparatuses, and methods for implementing a sampling circuit with increased headroom are disclosed. A sampling circuit includes at least a pair of input signal transistors connected via their drains to a cross-coupled pair of state nodes. The cross-coupled pair of state nodes are coupled to a tail transistor device via the sources of N-type transistors. When clock goes low, the circuit precharges the cross-coupled pair of state nodes while simultaneously attempting to amplify the difference between the pair of input signals. The amplification is performed by a pair of transistors in series between a source of each input signal transistor and ground. Each gate of the pair of transistors is connected to an inverted clock signal. When clock goes high, the circuit stops precharging and a voltage difference between the pair of input signals is regenerated to create a resulting differential voltage on the pair of state nodes.

US Patent:

20200344039, Oct 29, 2020

Filed:

Dec 10, 2019

Appl. No.:

16/709472

Inventors:

- Santa Clara CA, US
- Markham CA, US
Gerald R. Talbot - Concord MA, US
Gurunath Dollin - San Jose CA, US
Damon Tohidi - Richmond Hill, CA
Eric Ian Carpenter - Fort Collins CO, US
Chad S. Gallun - Austin TX, US
Jeffrey Cooper - Fort Collins CO, US
Hanwoo Cho - San Diego CA, US
Scott F. Dow - Fruita CO, US
Michael J. Tresidder - Spicewood TX, US

International Classification:

H04L 7/04
H04L 7/00

Abstract:

Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

US Patent:

20200312382, Oct 1, 2020

Filed:

Mar 28, 2019

Appl. No.:

16/368311

Inventors:

- Santa Clara CA, US
Jeffrey Cooper - Fort Collins CO, US

International Classification:

G11C 7/06
G11C 15/04

Abstract:

Systems, apparatuses, and methods for implementing a sampling circuit with increased headroom are disclosed. A sampling circuit includes at least a pair of input signal transistors connected via their drains to a cross-coupled pair of state nodes. The cross-coupled pair of state nodes are coupled to a tail transistor device via the sources of N-type transistors. When clock goes low, the circuit precharges the cross-coupled pair of state nodes while simultaneously attempting to amplify the difference between the pair of input signals. The amplification is performed by a pair of transistors in series between a source of each input signal transistor and ground. Each gate of the pair of transistors is connected to an inverted clock signal. When clock goes high, the circuit stops precharging and a voltage difference between the pair of input signals is regenerated to create a resulting differential voltage on the pair of state nodes.

US Patent:

20200280290, Sep 3, 2020

Filed:

Feb 28, 2019

Appl. No.:

16/289247

Inventors:

- Santa Clara CA, US
Jeffrey Cooper - Fort Collins CO, US

International Classification:

H03F 3/45

Abstract:

Systems, apparatuses, and methods for performing offset correction for pseudo differential signaling are disclosed. An apparatus includes at least a sense amplifier and an offset correction circuit. The offset correction circuit generates an offset correction voltage by applying a positive or negative offset to a termination voltage. The offset correction circuit supplies the offset correction voltage to a negative input terminal of the sense amplifier. An input signal voltage is supplied to the positive input terminal of the sense amplifier. The sense amplifier generates an output based on a comparison of the voltages supplied to the positive and negative input terminals.

US Patent:

20200099406, Mar 26, 2020

Filed:

Sep 24, 2018

Appl. No.:

16/140364

Inventors:

- Santa Clara CA, US
Milam Paraschou - Dellwood MN, US
Chad S. Gallun - Austin TX, US
Jeffrey Cooper - Fort Collins CO, US
Dean E. Gonzales - Fort Collins CO, US
Alushulla Jack Ambundo - Austin TX, US
Gerald R. Talbot - Concord MA, US

International Classification:

H04B 1/04
H04B 1/16
H01L 27/02
H03M 1/80

Abstract:

Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.

US Patent:

20120086494, Apr 12, 2012

Filed:

Oct 6, 2010

Appl. No.:

12/899191

Inventors:

Gladney ASADA - Santa Clara CA, US
Jeffrey COOPER - Ft. Collins CO, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

H03L 5/00

US Classification:

327307

Abstract:

Apparatus and methods are provided for calibrating and operating a receiver circuit. An exemplary method comprises the steps of applying a first voltage offset to a first input of an amplifier circuit, generating an output signal at an output of the amplifier circuit based on the first voltage offset and a second voltage offset at a second input of the amplifier circuit, adjusting the second voltage offset based on the output signal, and maintaining the second voltage offset at a constant voltage when the output signal is indicative of the second voltage offset cancelling the first voltage offset.