Jeffrey Jon Freeman

US Patent:

6701476, Mar 2, 2004

Filed:

May 29, 2001

Appl. No.:

09/870205

Inventors:

Bahram Pouya - Austin TX
Alfred L. Crouch - Cedar Park TX
Gregory Dean Young - Georgetown TX
Jeffrey L. Freeman - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G01R 3128

US Classification:

714727, 714729, 714731

Abstract:

A configurable test access mechanism has a sliced input wrapper, output wrapper and scan configuration wrapper coupled to a circuit under test. The input wrapper efficiently adds a PRPG (pseudo-random pattern generator) function to a scan test structure without impacting speed and power requirements. The output wrapper efficiently adds a MISR (multiple input signature register) functionality for additional test purposes to implement a built-in self-test (BIST) apparatus. Use of existing scan structures to implement the PRPG and MISR functions provides significant savings of circuitry. Variability of test polynomials is easily user programmed.

US Patent:

20200272594, Aug 27, 2020

Filed:

May 15, 2019

Appl. No.:

16/412746

Inventors:

- AUSTIN TX, US
George Adrian Ciusleanu - Marasesti, RO
David Allen Brown - Austin TX, US
Jeffrey Freeman - Austin TX, US

International Classification:

G06F 15/78

Abstract:

An integrated circuit is disclosed that includes a central processing unit (CPU), a random access memory (RAM) configured for storing data and CPU executable instructions, a first peripheral circuit for accessing memory that is external to the integrated circuit, a second peripheral circuit, and a communication bus coupled to the CPU, the RAM, the first peripheral circuit and the second peripheral circuit. The second peripheral circuit includes a first preload register configured to receive and store a first preload value, a first register configured to store first information that directly or indirectly identifies a first location where first instructions of a first task can be found in memory that is external to the integrated circuit, and a counter circuit that includes a counter value. The counter circuit can increment or decrement the counter value with time when the counter circuit is started. A first compare circuit is also included and can compare the counter value to the first preload value. The first compare circuit is configured to assert a first match signal in response to detecting a match between the counter value and the first preload value. The second peripheral circuit is configured to send a first preload request to the first peripheral circuit in response to an assertion of the first match signal. The first preload request identifies the location where the first instructions of the first task can be found in the external memory.

US Patent:

20190370211, Dec 5, 2019

Filed:

Jun 1, 2018

Appl. No.:

15/995881

Inventors:

- Austin TX, US
Jeffrey Freeman - Austin TX, US

International Classification:

G06F 15/17
G06F 9/38
G06F 15/78
G06F 13/42

Abstract:

A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to first connectivity circuitry by a first processor bus and configured to provide first bus transactions to the first processor bus, the discrete signal lines connected to the first connectivity circuitry to provide first discrete signals indicative of discrete events, the first connectivity circuitry configured to store the first discrete signals in a plurality of virtual signal registers and to convert the first bus transactions and the first discrete signals into die-to-die message packets to be communicated to the second connectivity circuitry via a die-to-die interconnect between the first die and the second die, the first discrete signals being converted into the die-to-die message packets on a register-by-register basis.

US Patent:

20190370212, Dec 5, 2019

Filed:

Jun 1, 2018

Appl. No.:

15/995983

Inventors:

- Austin TX, US
Jeffrey Freeman - Austin TX, US
Huy Nguyen - Austin TX, US

International Classification:

G06F 15/17
G06F 13/42
G06F 15/78
G06F 9/38
G06K 9/62

Abstract:

A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to the first connectivity circuitry by the first processor bus and configured to provide first bus transactions, to be provided to the second connectivity circuitry, to the first processor bus, the first connectivity circuitry configured to utilize a multiple simultaneous outstanding transaction capability supporting multiple simultaneous outstanding write transactions concurrent with multiple simultaneous outstanding read transactions, the second connectivity circuitry configured to provide processor bus flow control information and elasticity buffer status information pertaining to the elasticity buffer to the first connectivity circuitry via a common message for flow control.

US Patent:

20150089305, Mar 26, 2015

Filed:

Mar 12, 2012

Appl. No.:

14/382593

Inventors:

Markus Baumeister - Munich, DE
Jeffrey L. Freeman - Austin TX, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

G06F 11/07

US Classification:

714 51

Abstract:

An interrupt supervision system comprises an interrupt controller device comprising a plurality of interrupt request input lines and at least one output line connectable to a processing device. The interrupt controller device is arranged to receive, on the plurality of interrupt request input lines, a plurality of corresponding interrupt requests and to provide, on the at least one output line, the plurality of interrupt requests to the processing device in a sequence generated by the interrupt controller device depending on one or more priorities assigned to the interrupt requests; and one or more interrupt checker devices, each being arranged to receive a reception indication when the interrupt controller device receives, on a selected one of the plurality of interrupt request lines, a corresponding selected interrupt request, and to provide a corresponding error indication when an output of the corresponding selected interrupt request from the interrupt controller device on the at least one output line is not confirmed within a latency period assigned to the corresponding selected interrupt request, wherein the assigned latency period begins when the interrupt checker device receives the reception indication.