Jeffrey L Gilbert

US Patent:

6552411, Apr 22, 2003

Filed:

Mar 16, 2001

Appl. No.:

09/809887

Inventors:

Arne W. Ballantine - Round Lake NY
John J. Ellis-Monaghan - Grande Isle VT
Jeffrey D. Gilbert - South Burlington VT
Glenn R. Miller - Essex Junction VT
James A. Slinkman - Montpelier VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2900

US Classification:

257530, 257422, 438510, 438659, 438660, 438514, 438572, 118500, 204164

Abstract:

A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

US Patent:

6670263, Dec 30, 2003

Filed:

Mar 10, 2001

Appl. No.:

09/802702

Inventors:

Arne W. Ballantine - Round Lake NY
Kevin K. Chan - Staten Island NY
Jeffrey D. Gilbert - Burlington VT
Kevin M. Houlihan - Boston MA
Glen L. Miles - Essex Junction VT
James J. Quinlivan - Essex Junction VT
Samuel C. Ramac - Poughkeepsie NY
Michael B. Rice - Colchester VT
Beth A. Ward - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 213205

US Classification:

438592, 438585, 438199, 438287, 438655

Abstract:

Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

US Patent:

6822311, Nov 23, 2004

Filed:

Apr 15, 2003

Appl. No.:

10/413301

Inventors:

Arne W. Ballantine - Round Lake NY
John J. Ellis-Monaghan - Grande Isle VT
Jeffrey D. Gilbert - South Burlington VT
Glenn R. Miller - Essex Junction VT
James A. Slinkman - Montpelier VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2900

US Classification:

257530, 257529, 257531, 257532, 438729, 438730, 438731, 216 67, 216 71, 156345

Abstract:

A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneously exposing the semiconductor substrate to an electric field.

US Patent:

6893948, May 17, 2005

Filed:

Jul 11, 2003

Appl. No.:

10/616962

Inventors:

Arne W. Ballantine - Round Lake NY, US
Kevin K. Chan - Staten Island NY, US
Jeffrey D. Gilbert - Burlington VT, US
Kevin M. Houlihan - Boston MA, US
Glen L. Miles - Essex Junction VT, US
James J. Quinlivan - Essex Junction VT, US
Samuel C. Ramac - Essex Junction VT, US
Michael B. Rice - Colchester VT, US
Beth A. Ward - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L021/20
H01L021/3205
H01L021/4763

US Classification:

438585, 438592, 438488

Abstract:

Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting structure may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size is directed to maximize dopant activation in the polysilicon near the gate dielectric, and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. This method, and the resulting structure, are advantageously employed in forming FETs, and doped polysilicon resistors.

US Patent:

7714366, May 11, 2010

Filed:

Nov 16, 2004

Appl. No.:

10/904565

Inventors:

Arne W. Ballantine - Round Lake NY, US
Kevin K. Chan - Staten Island NY, US
Jeffrey D. Gilbert - Burlington VT, US
Kevin M. Houlihan - Boston MA, US
Glen L. Miles - Essex Junction VT, US
James J. Quinlivan - Essex Junction VT, US
Samuel C. Ramac - Poughkeepsie NY, US
Michael B. Rice - Colchester VT, US
Beth A. Ward - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/088
H01L 29/78

US Classification:

257288, 257407, 257413, 257E21197, 257E21412, 257E29155

Abstract:

Polysilicon electrical depletion in a polysilicon gate electrode is reduced by depositing the polysilicon under controlled conditions so as to vary the crystal grain size through the thickness of the polysilicon. The resulting CMOS transistor may have two or more depth-wise contiguous regions of respective crystalline grain size, and the selection of grain size may be directed to maximize dopant activation in the polysilicon near the gate dielectric and to tailor the resistance of the polysilicon above that first region and more distant from the gate dielectric. A region of polycrystalline silicon may have a varying grain size as a function of a distance measured from a surface of the dielectric film.

US Patent:

20020182893, Dec 5, 2002

Filed:

Jun 5, 2001

Appl. No.:

09/874144

Inventors:

Arne Ballantine - Round Lake NY, US
Johnathan Faltermeier - LaGrangeville NY, US
Philip Flaitz - Newburgh NY, US
Jeffrey Gilbert - South Burlington VT, US
Oleg Gluschenkov - Wappingers Falls NY, US
Carol Heenan - LaGrangeville NY, US
Rajarao Jammy - Wappingers Falls NY, US
Ryota Katsumada - Isogo-ku, JP

Assignee:

International Business Machines Corporation - Armonk NJ

International Classification:

H01L021/31
H01L021/469
H01L021/26
H01L021/324
H01L021/42
H01L021/477

US Classification:

438/795000, 438/787000

Abstract:

Disclosed is a method to convert a stable silicon nitride film into a stable silicon oxide film with a low content of residual nitrogen in the resulting silicon oxide film. This is an unexpected and unique property of the in situ steam generation process since both silicon nitride and silicon oxide materials are chemically very stable compounds. Application of the claimed method to the art of microelectronic device fabrication, such as fabrication of on-chip dielectric capacitors and metal insulator semiconductor field effect transistors, is also disclosed.