Jeffrey P Hammes

US Patent:

6964029, Nov 8, 2005

Filed:

Oct 31, 2002

Appl. No.:

10/285298

Inventors:

Daniel Poznanovic - Colorado Springs CO, US
Jeffrey Hammes - Colorado Springs CO, US
Lisa Krause - Minneapolis MN, US
Jon Steidel - Minneapolis MN, US

Assignee:

SRC Computers, Inc. - Colorado Springs CO

International Classification:

G06F009/45

US Classification:

716 7

Abstract:

An embodiment of the invention includes a system for partitioning a control-flow graph representation into a reconfigurable portion and an instruction processor portion. Another embodiment of the invention includes a method of partitioning a control-dataflow graph representation that includes dividing the control-dataflow graph into two or more partition blocks, comparing the estimated performance of at least one of the partition blocks as reconfigurable logic versus instruction processor code; and assigning said at least one of the partition blocks to reconfigurable hardware or an instruction processor based on said comparing step.

US Patent:

6983456, Jan 3, 2006

Filed:

Oct 31, 2002

Appl. No.:

10/285299

Inventors:

Daniel Poznanovic - Colorado Springs CO, US
Jeffrey Hammes - Colorado Springs CO, US
Lisa Krause - Minneapolis MN, US
Jon Steidel - Minneapolis MN, US
David Barker - Salinas CA, US
Jeffrey Paul Brooks - St. Louis MN, US

Assignee:

SRC Computers, Inc. - Colorado Springs CO

International Classification:

G06F 9/44

US Classification:

717133, 717132, 717156

Abstract:

A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation. The driver invokes a hardware description language (HDL) compiler to produce a netlist file that can be used to start the place-and-route compilation needed to produce a bitstream for the reconfigurable computer. The programming environment then provides support for taking the output from the compilation driver and combining all the necessary components together to produce a unified executable capable of running on both the instruction processor and reconfigurable processor.

US Patent:

7134120, Nov 7, 2006

Filed:

Jan 14, 2003

Appl. No.:

10/345082

Inventors:

Jeffrey Hammes - Colorado Springs CO, US

Assignee:

SRC Computers, Inc. - Colorado Springs CO

International Classification:

G06F 9/45

US Classification:

717155, 717150, 717156, 717157

Abstract:

A control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, a loop valid node coupled to the loop body that determines a final loop iteration, and an output value storage node coupled to the circulate node, where the output value storage node ignores output values generated after the loop valid node determines the final loop iteration has occurred. Also, a control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, and a loop driver node coupled to the circulate node, where the loop driver node sets a period for each iteration of the loop body.

US Patent:

7149867, Dec 12, 2006

Filed:

Jun 16, 2004

Appl. No.:

10/869200

Inventors:

Daniel Poznanovic - Colorado Springs CO, US
David E. Caliga - Colorado Springs CO, US
Jeffrey Hammes - Colorado Springs CO, US

Assignee:

SRC Computers, Inc. - Colorado Springs CO

International Classification:

G06F 12/00

US Classification:

711170, 711154

Abstract:

A reconfigurable processor that includes a computational unit and a data prefetch unit coupled to the computational unit, where the data prefetch unit retrieves data from a memory and supplies the data to the computational unit through memory and a data access unit, and where the data prefetch unit, memory, and data access unit is configured by a program. Also, a reconfigurable hardware system that includes a common memory; and one or more reconfigurable processors coupled to the common memory, where at least one of the reconfigurable processors includes a data prefetch unit to read and write data between the unit and the common memory, and where the data prefetch unit is configured by a program executed on the system. In addition, a method of transferring data that includes transferring data between a memory and a data prefetch unit in a reconfigurable processor; and transferring the data between a computational unit and the data prefetch unit.

US Patent:

7155708, Dec 26, 2006

Filed:

Oct 31, 2002

Appl. No.:

10/285389

Inventors:

Jeffrey Hammes - Colorado Springs CO, US
Daniel Poznanovic - Colorado Springs CO, US
Lonnie Gliem - Burnsville MN, US

Assignee:

SRC Computers, Inc. - Colorado Springs CO

International Classification:

G06F 9/45
G06F 9/44

US Classification:

717155, 717156, 717157, 717135, 717132

Abstract:

An embodiment of the invention includes a method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm which utilizes a runtime selectable emulation library that emulates a reconfigurable processor and its resources, and a control-data flow emulator that emulates the reconfigurable logic for the algorithm. Another embodiment of the invention includes a method of simulating a control-dataflow graph that includes building an internal representation of the control-dataflow graph that includes one or more dataflow code blocks, and simulating the control-dataflow graph as a sequence of code block dataflow executions, where control is passed from one code block to another code block based on the output value of the code block until EXIT is reached.

US Patent:

7299458, Nov 20, 2007

Filed:

Oct 31, 2002

Appl. No.:

10/285399

Inventors:

Jeffrey Hammes - Colorado Springs CO, US

Assignee:

SRC Computers, Inc. - Colorado Springs CO

International Classification:

G06F 9/44

US Classification:

717133, 717132, 717156, 716 7

Abstract:

An embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, and converting said two or more basic blocks into code blocks, where the code blocks are formed into the control-dataflow graph. Another embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, forming a lode node in at least one of said basic blocks, forming a store node in at least one of said code blocks, inserting a delay node in at least one of said code blocks, segregating external hardware logic modules from said control flow graph, and converting said two or more basic blocks into code blocks, wherein the code blocks are formed into the control-dataflow graph.

US Patent:

7703085, Apr 20, 2010

Filed:

Oct 4, 2005

Appl. No.:

11/243498

Inventors:

Daniel Poznanovic - Colorado Springs CO, US
Jeffrey Hammes - Colorado Springs CO, US
Lisa Krause - Minneapolis MN, US
Jon Steidel - Minneapolis MN, US
David Barker - Salinas CA, US
Jeffrey Paul Brooks - St. Louis MN, US

Assignee:

SRC Computers, Inc. - Colorado Springs CO

International Classification:

G06F 9/45
G00O 9/44

US Classification:

717140, 717141, 717154

Abstract:

A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), and the associated support code for managing execution on a hybrid hardware platform. Explicit knowledge of writing hardware-level design code is not required since the problem can be represented in a high-level language syntax. A top-level driver invokes a standard-conforming compiler that provides syntactic and semantic analysis. The driver invokes a compilation phase that translates the CFG representation being generated into a hybrid controlflow-dataflow graph representation representing optimized pipelined logic which may be processed into a hardware description representation. The driver invokes a hardware description language (HDL) compiler to produce a netlist file that can be used to start the place-and-route compilation needed to produce a bitstream for the reconfigurable computer. The programming environment then provides support for taking the output from the compilation driver and combining all the necessary components together to produce a unified executable capable of running on both the instruction processor and reconfigurable processor.

US Patent:

8589666, Nov 19, 2013

Filed:

Jul 10, 2006

Appl. No.:

11/456466

Inventors:

Jeffrey Hammes - Colorado Springs CO, US

Assignee:

SRC Computers, Inc. - Colorado Springs CO

International Classification:

G06F 15/00
G06F 7/38
G06F 9/00
G06F 9/44

US Classification:

712241, 714 18

Abstract:

A reconfigurable processor invoking data stream pipelining is configured to associate a restore buffer with each incoming data stream. The buffer is configured to be of sufficient size to maintain data values dispatched to a loop so as to restore values fetched and lost due to loop overshoots. The restore buffer stores the values that were recently fetched from the buffer to the loop. To determine how many data values should be restored, the loop counts the number of the data values it takes from each data stream and the number of valid loop iterations that take place. Once a loop termination is detected, the loop halts the fetching of values from the restore buffer and compares, for each stream, the number of loop iterations with the number of values fetched. The difference is the number of extra values that were taken from the restore buffer and are restored.