Jeffrey R Irwin

US Patent:

7068278, Jun 27, 2006

Filed:

Dec 11, 2003

Appl. No.:

10/732944

Inventors:

Ian M. Williams - Menlo Park CA, US
Dale Ah Tye - Redwood City CA, US
Jeffrey J. Irwin - Sunnyvale CA, US
John S. Montrym - Cupertino CA, US
Michael Diamond - Los Gatos CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 1/20
G09G 5/399

US Classification:

345506, 345539, 713400

Abstract:

A graphics processing unit, which includes a clock generator configured to generate a clock signal and a controller coupled to the clock generator. The controller is configured to receive the clock signal, compare the clock signal with a synchronization signal to generate a timing signal, and transmit the timing signal to a second graphics processing unit connected to the graphics processing unit.

US Patent:

7315957, Jan 1, 2008

Filed:

Dec 18, 2003

Appl. No.:

10/742444

Inventors:

Barry Wagner - San Jose CA, US
Jonah M. Alben - San Jose CA, US
Sonny Yeoh - San Jose CA, US
Jeffrey J. Irwin - Sunnyvale CA, US
Saurabh Gupta - Santa Clara CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 1/00

US Classification:

713501, 713500, 713502

Abstract:

Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selected to provide a memory clock signal to the graphics memory. The multiplexer switches from providing a first clock source signal as the memory clock signal to providing a second clock source signal as the memory clock signal. The first clock source changes its frequency of operation. After the first clock source settles or stabilizes, the multiplexer switches back to providing the first clock source signal as the memory clock signal.

US Patent:

7657775, Feb 2, 2010

Filed:

Nov 22, 2007

Appl. No.:

11/944429

Inventors:

Barry Wagner - San Jose CA, US
Jonah M. Alben - San Jose CA, US
Sonny Yeoh - San Jose CA, US
Jeffrey J. Irwin - Sunnyvale CA, US
Saurabh Gupta - Santa Clara CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 1/00
H03L 7/00
H03B 5/12

US Classification:

713501, 327144, 331 49

Abstract:

Methods, circuits, and apparatus for changing a frequency of a clock signal provided to a graphics memory while reducing any resulting visual glitch or disturbance on a monitor. A specific embodiment provides multiple clock sources that may be multiplexed or selected to provide a memory clock signal to the graphics memory. The multiplexer switches from providing a first clock source signal as the memory clock signal to providing a second clock source signal as the memory clock signal. The first clock source changes its frequency of operation. After the first clock source settles or stabilizes, the multiplexer switches back to providing the first clock source signal as the memory clock signal.

US Patent:

20230081975, Mar 16, 2023

Filed:

Sep 16, 2021

Appl. No.:

17/476704

Inventors:

- Cupertino CA, US
Felix C. Fernandes - Saratoga CA, US
Jeffrey J. Irwin - Cupertino CA, US
Liviu R. Morogan - San Jose CA, US
Sorin Constantin Cismas - Saratoga CA, US

International Classification:

H04N 19/436
H04N 19/423

Abstract:

Systems and methods of parallel image parsing and processing for video decoding are provided. Video decoder circuitry may enable an incoming encoded bitstream to be split into multiple bitstreams corresponding to the bitstream compression scheme and processed by multiple parsers corresponding to the bitstream compression scheme in parallel. This enables parallel decoding of the incoming bitstream and, thus, more efficient decoder processing.

US Patent:

20150310900, Oct 29, 2015

Filed:

Apr 25, 2014

Appl. No.:

14/262298

Inventors:

- Cupertino CA, US
Jeffrey J. Irwin - Cupertino CA, US
Peter F. Holland - Los Gatos CA, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 7/10

Abstract:

Systems, apparatuses, and methods for aggregating memory requests with opportunism in a display pipeline. Memory requests are aggregated for each requestor of a plurality of requestors in the display pipeline. When the number of memory requests for a given requestor reaches a corresponding threshold, memory requests may be issued for the given requestor. In response to determining the given requestor has reached its threshold, other requestors may issue memory requests even if they have not yet aggregated enough memory requests to reach their corresponding thresholds.