Jeffrey R Leonard

US Patent:

6594803, Jul 15, 2003

Filed:

Sep 24, 1999

Appl. No.:

09/406016

Inventors:

Laura A. Weber - Austin TX
Fritz A. Boehm - Dripping Springs TX
Jean Anne Booth - Austin TX
Terri Lynn Fukuhara - Austin TX
Jeffrey S. Leonard - Austin TX
Shawn D. Strawbridge - Austin TX
Douglas N. Good - Austin TX

Assignee:

Intrinsity, Inc. - Austin TX

International Classification:

G06F 1705

US Classification:

716 5, 716 4

Abstract:

The present invention is a grid that is a monitor that detects a cross product of design verification events and reports a single status event to a database. One embodiment of the present invention comprises axes declarations, logic expressions, and a grid declaration. An axes declaration produces a cross product of verification events. A logic expressions evaluates whether a specific verification event has occurred. A grid declaration returns the status event. The present invention further comprises a grid where the cross-product of verification events comprises a fully or a sparsely populated cross-product of verification events. Additionally, the present invention further comprises a grid that uses N-Nary signals. And, the present invention comprises a parser to translate the monitor source file code into a standard computer language code.

US Patent:

6889180, May 3, 2005

Filed:

Sep 24, 1999

Appl. No.:

09/406017

Inventors:

Laura A. Weber - Austin TX, US
Fritz A. Boehm - Dripping Springs TX, US
Jean Anne Booth - Austin TX, US
Jeffrey S. Leonard - Austin TX, US
Shawn D. Strawbridge - Austin TX, US
Douglas N. Good - Austin TX, US

Assignee:

Intrinsity, Inc. - Austin TX

International Classification:

G06F017/50

US Classification:

703 16, 703 15, 716 18

Abstract:

The present invention is a monitor that detects a design verification event and reports a status event to a database. One embodiment of the present invention comprises a monitor declaration, zero or more signal declarations, zero or more bus declarations and one or more logic expressions. A logic expression, formulated using the declared signals and buses, is used to evaluate whether a specific verification event has occurred. The present invention further comprises a monitor where the signal of the signal declaration of the monitor is an N-Nary signal. Additionally, the present invention comprises a parser to translate the monitor source file code into a standard computer language code.