Jeffrey H Lin

US Patent:

6424559, Jul 23, 2002

Filed:

Sep 29, 2000

Appl. No.:

09/675616

Inventors:

Jeffrey Lin - Danville CA

Assignee:

JMOS Technology, Inc. - Fremont CA

International Classification:

G11C 1124

US Classification:

365149, 365190, 365205

Abstract:

A method and apparatus for sense amplification is disclosed. In one embodiment, this is a method of amplifying signals in a DRAM including sharing charge between a cell and a first conductor of a first pair of complementary conductors; and driving a voltage of the first conductor of the first pair and a voltage of a second conductor of the first pair in the same direction relative to a power supply voltage. In an alternate embodiment, this is an apparatus. The apparatus includes a first transistor having a first terminal, a second terminal and a gate. The apparatus also includes a second transistor having a first terminal, a second terminal and a gate, the gate of the second transistor coupled to the first terminal of the first transistor, the first terminal of the second transistor coupled to the gate of the first transistor. Moreover, the apparatus also includes a third transistor having a first terminal, a second terminal, and a gate, the first terminal of the third transistor coupled to the second terminal of the first transistor and the second terminal of the second transistor, the gate of the third transistor coupled to a power enable conductor, the second terminal of the third transistor coupled to a power supply node. In another alternate embodiment, this is a DRAM cell array.

US Patent:

6459650, Oct 1, 2002

Filed:

May 15, 2001

Appl. No.:

09/858832

Inventors:

Jeffrey Lin - Danville CA

Assignee:

JMOS Technology, Inc. - Fremont CA

International Classification:

G11C 800

US Classification:

365233, 36518901, 365222

Abstract:

A method and apparatus for asynchronously controlling a DRAM array in an SRAM environment is described. In on embodiment, this is a method of arbitrating between a refresh request and an access request. Furthermore, the access request may be either a read or a write request. Moreover, the request may be generated by a refresh control circuit within a circuit implementing the asynchronous control method. In an alternate embodiment, this is an apparatus. The apparatus includes an arbitration circuit block which may receive a refresh request and an access request. Furthermore, the access request may come as a read request or a write request, which may be implemented as separate signals. Moreover, the apparatus may include a refresh circuit block which may generate refresh control signals and the refresh request signal for the arbitration circuit.

US Patent:

8371704, Feb 12, 2013

Filed:

Oct 24, 2011

Appl. No.:

13/279756

Inventors:

Jeffrey Lin - Cupertino CA, US

Assignee:

Google Inc. - Mountain View CA

International Classification:

G02B 27/00

US Classification:

359613

Abstract:

An electronic device includes a display unit and a filter. The display unit is configured to provide a visual display to a user of the device. The display unit has a first side portion and a second side portion. The filter is configured to alter a viewer's perception of the visual display. The filter is pivotally coupled to the display unit. The filter is configured to pivot from a first position adjacent the first side portion of the display unit to a second position adjacent the second side portion of the display unit.

US Patent:

8400764, Mar 19, 2013

Filed:

Sep 28, 2011

Appl. No.:

13/247967

Inventors:

Jeffrey Lin - Cupertino CA, US

Assignee:

Google Inc. - Mountain View CA

International Classification:

H05K 7/00

US Classification:

36167924, 36167901, 36167902

Abstract:

A device includes a display unit, a first coupler, and a second coupler. The display unit is configured to provide a visual display to a user of the device. The display unit has a first side portion and a second side portion. The first coupler is disposed on the first side portion of the display unit. The first coupler is configured to removably couple a filter to the first side portion of the display unit. The second coupler is disposed on the second side portion of the display unit. The second coupler is configured to removably couple the filter to the second side portion of the display unit.

US Patent:

57038279, Dec 30, 1997

Filed:

Feb 29, 1996

Appl. No.:

8/610108

Inventors:

Wingyu Leung - Cupertino CA
Jeffrey J. Lin - Danville CA

Assignee:

Monolithic System Technology, Inc. - Sunnyvale CA

International Classification:

G11C 700

US Classification:

36523006

Abstract:

A method and structure for generating a boosted word line voltage for a memory array, such as a DRAM array. To ensure that an adequate voltage is applied to the word line of the memory array during write operations, the word line driver circuit is connected to a boost voltage generator which provides a substantially constant, regulated voltage which is boosted to a level which is approximately equal to the V. sub. CC supply voltage plus the threshold voltage of the memory cell pass transistor. A bias voltage generator provides a negative voltage which is used to bias the substrate of the memory array. The boosted voltage generator and the bias voltage generator can be operated in response to the same clock signal used to operate the memory array. A latch-up prevention circuit is provided to ensure that the word line driver circuit does not latch-up during power-on before an adequate boost voltage has been established.

US Patent:

58055096, Sep 8, 1998

Filed:

Jul 10, 1997

Appl. No.:

8/891124

Inventors:

Wingyu Leung - Cupertino CA
Jeffrey J. Lin - Danville CA

Assignee:

Monolithic System Technology, Inc. - Sunnyvale CA

International Classification:

H03K 301

US Classification:

36518909

Abstract:

A method and structure for generating a boosted word line voltage for a memory array, such as a DRAM array. To ensure that an adequate voltage is applied to the word line of the memory array during write operations, the word line driver circuit is connected to a boost voltage generator which provides a substantially constant, regulated voltage which is boosted to a level which is approximately equal to the V. sub. cc supply voltage plus the threshold voltage of the memory cell pass transistor. A bias voltage generator provides a negative voltage which is used to bias the substrate of the memory array. The boosted voltage generator and the bias voltage generator can be operated in response to the same clock signal used to operate the memory array. A latch-up prevention circuit is provided to ensure that the word line driver circuit does not latch-up during power-on before an adequate boost voltage has been established.

US Patent:

20210260584, Aug 26, 2021

Filed:

Feb 4, 2021

Appl. No.:

17/167949

Inventors:

- San Mateo CA, US
Jeffrey LIN - Palo Alto CA, US

International Classification:

B01L 3/00

Abstract:

The present disclosure provides microfluidic device comprising microfluidic valves with low or substantially no dead volume. The valves may comprise an actuation layer, a fluidic layer and a membrane between the actuation layer and the fluidic layer. The fluidic layer may comprise a fluidic channel, which fluidic channel may have a cross-sectional area having a curved shape. The actuation layer may be configured to apply positive or negative pressure to the membrane to deflect the membrane towards or away from the fluidic layer. The membrane may comprise one or more polymeric layers.

US Patent:

20170177589, Jun 22, 2017

Filed:

Dec 17, 2015

Appl. No.:

14/973673

Inventors:

- Menlo Park CA, US
Jiawen Connie Yang - Menlo Park CA, US
Eric Andrew Shrewsberry - Palo Alto CA, US
Wei Zhong Yeh - East Palo Alto CA, US
Jason Fotinatos - Cupertino CA, US
Dustin S. Ho - Palo Alto CA, US
Jack Murray - Menlo Park CA, US
Jeffrey Lin - Palo Alto CA, US
Alisha S. Outridge - San Francisco CA, US

International Classification:

G06F 17/30
H04L 29/08
H04L 12/58
H04L 29/06

Abstract:

In one embodiment, a method includes accessing one or more content objects associated with a first user of an online social network; generating a set of tag candidates by extracting one or more n-grams from the content objects, wherein each tag candidate comprises one or more text strings or ideograms from the extracted n-grams; calculating, for each tag candidate of the set of tag candidates, a quality-score for the tag candidate based on an affinity coefficient between the first user and a respective content object from which the n-grams or ideograms comprising the tag candidate were extracted; and sending, to a client system for display, one or more of the tag candidates as suggested tags for the first user, wherein each suggested tag has a quality-score greater than a threshold quality-score.