Jeffrey Scott Myers

US Patent:

6385113, May 7, 2002

Filed:

Apr 30, 1999

Appl. No.:

09/303284

Inventors:

Michael L. Longwell - Austin TX
William Daune Atwell - Spicewood TX
Jeffrey Van Myers - Driftwood TX

Assignee:

Madrone Solutions, Inc - Spicewood TX

International Classification:

G11C 700

US Classification:

365222, 36523003, 365149

Abstract:

A method for operating a dynamic memory ( ) in a sleep mode. The method writes a predetermined background value to at least a background portion of the memory, and then ceases to refresh the background portion. The background value corresponds to the conductivity type of the memory cell, where N-channel devices have a low value and P-channel devices have a high value. After return from sleep mode, the voltage reference is not impacted by the residual charge in the memory cells. According to one embodiment, a refresh controller ( ) accesses a look up table ( ) to store data indicating the status of memory cells. Prescaling may then adjust the period and duty cycle of the refresh cycle in response to the inactive wordlines via a unit, such as prescaler ( ). In one embodiment, the background value is written to the inactive memory cell ( ) via sense amplifier killer circuitry ( ).

US Patent:

6552947, Apr 22, 2003

Filed:

Apr 5, 1999

Appl. No.:

09/286196

Inventors:

Michael L. Longwell - Austin TX
William Daune Atwell - Spicewood TX
Jeffrey Van Myers - Driftwood TX

Assignee:

Madrone Solutions, Inc. - Austin TX
Motorola, Inc. - Shaumburg IL

International Classification:

G11C 700

US Classification:

365226, 365200, 36523003

Abstract:

A plurality of memory tiles ( ) are arranged to form a tiled memory array ( ) in an integrated circuit device ( ). In accordance with the present invention, each of the memory tiles ( ) in the tiled memory array ( ) has charge source circuitry ( ) to provide the sufficient reference voltages for proper operation of the memory tile ( ). In addition, each memory tile ( ) may include local error detection and correction circuitry ( ). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry ( â).

US Patent:

6560725, May 6, 2003

Filed:

Jun 18, 1999

Appl. No.:

09/335992

Inventors:

Michael L. Longwell - Austin TX
William Daune Atwell - Spicewood TX
Jeffrey Van Myers - Driftwood TX

Assignee:

Madrone Solutions, Inc. - Austin TX

International Classification:

G06F 1100

US Classification:

714 54, 714 48, 714704, 714718, 714763, 714764, 711105, 711106

Abstract:

A method for tracking errors in a memory system by detecting an error in a bit of a word accessed in the memory and maintaining an error history comprising a record of each of the detected errors. The error history information may be used to configure the memory, such as to add redundancy; or may be used to adjust operating parameters of the memory, such as the periodicity of refresh and/or scrub operations; or may be used to trigger a sensing operation of other parameters in an application system. In one embodiment, a counter increments each time an error is detected and decrements when no error is detected, thereby tracking error patterns.

US Patent:

7134069, Nov 7, 2006

Filed:

Jun 16, 1999

Appl. No.:

09/334238

Inventors:

Michael L. Longwell - Austin TX, US
William Daune Atwell - Spicewood TX, US
Jeffrey Van Myers - Driftwood TX, US

Assignee:

Madrone Solutions, Inc. - Spicewood TX

International Classification:

G06F 11/00
G11C 29/00

US Classification:

714800, 714763

Abstract:

A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a WEDAC operates in coordination with a full bit-wise BEDAC that calculates bit-wise check bits. The RAEDAC may be applied to create a multi-dimensional EDAC where, for example, the memory is partitioned into a stack of planes, and a stack-wise error detection and correction unit (SEDAC) is implemented.

US Patent:

7152240, Dec 19, 2006

Filed:

Jul 25, 2000

Appl. No.:

09/624923

Inventors:

Stuart D. Green - Leander TX, US
Scott G. Brown - Austin TX, US
Jonathan M. Crain - Kyle TX, US
Jeffrey Van Myers - Driftwood TX, US
Carl A. Perry - Florence TX, US
Marcus L. Yax - Austin TX, US

International Classification:

H04L 9/00
G06F 15/16
G06F 11/30
G06N 5/04

US Classification:

726 4, 726 13, 726 22, 709224, 706 60

Abstract:

A FireNet security system in which trustworthy networks, called BlackNets, each comprising One (1) or more client computers, are protected by FireBreaks against attacks from untrustworthy networks, called RedNets. All incoming transactions from the RedNet are examined by the FireBreak to determine if they violate any of a plurality of protection rules stored in a local protection rules database. Any transaction found to be in violation is discarded. Valid transactions are forwarded to the BlackNet. If an otherwise valid transaction is found to be suspicious, the FireBreak will forward to a FireNet Server relevant information relating to that transaction. If the FireNet Server verifies that the transaction is indeed part of an attack, the FireNet Server will create new protection rules suitable to defend against the newly identified source or strategy of attack. Periodically, all FireBreaks in the FireNet system will transfer, directly or indirectly, all new rules.

US Patent:

7644348, Jan 5, 2010

Filed:

Sep 11, 2006

Appl. No.:

11/518824

Inventors:

Michael L. Longwell - Austin TX, US
William Daune Atwell - Spicewood TX, US
Jeffrey Van Myers - Driftwood TX, US

Assignee:

Madrone Solutions, Inc. - Spicewood TX

International Classification:

G06F 11/00
G11C 29/00

US Classification:

714800, 714763

Abstract:

A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a WEDAC operates in coordination with a full bit-wise BEDAC that calculates bit-wise check bits. The RAEDAC may be applied to create a multi-dimensional EDAC where, for example, the memory is partitioned into a stack of planes, and a stack-wise error detection and correction unit (SEDAC) is implemented.

US Patent:

7716717, May 11, 2010

Filed:

Nov 6, 2006

Appl. No.:

11/593226

Inventors:

Stuart D. Green - Leander TX, US
Scott G. Brown - Austin TX, US
Jonathan M. Crain - Kyle TX, US
Jeffrey Van Myers - Driftwood TX, US
Carl A. Perry - Florence TX, US
Marcus L. Yax - Austin TX, US

International Classification:

G06F 21/00
G06F 7/00
G06F 15/16

US Classification:

726 1, 726 2

Abstract:

A FireNet security system in which trustworthy networks, called BlackNets, each comprising One (1) or more client computers, are protected by FireBreaks against attacks from untrustworthy networks, called RedNets. All incoming transactions from the RedNet are examined by the FireBreak to determine if they violate any of a plurality of protection rules stored in a local protection rules database. Any transaction found to be in violation is discarded. Valid transactions are forwarded to the BlackNet. If an otherwise valid transaction is found to be suspicious, the FireBreak will forward to a FireNet Server relevant information relating to that transaction. If the FireNet Server verifies that the transaction is indeed part of an attack, the FireNet Server will create new protection rules suitable to defend against the newly identified source or strategy of attack. Periodically, all FireBreaks in the FireNet system will transfer, directly or indirectly, all new rules.

US Patent:

8245274, Aug 14, 2012

Filed:

May 11, 2010

Appl. No.:

12/777570

Inventors:

Stuart D. Green - Leander TX, US
Scott G. Brown - Austin TX, US
Jonathan M. Crain - Kyle TX, US
Jeffrey Van Myers - Driftwood TX, US
Carl A. Perry - Florence TX, US
Marcus L. Yax - Austin TX, US

Assignee:

Tri MBC Communications L.L.C. - Wilmington DE

International Classification:

G06F 21/00
G06F 7/00
G06F 15/16

US Classification:

726 1, 726 2

Abstract:

A FireNet security system in which trustworthy networks, called BlackNets, each comprising One (1) or more client computers, are protected by FireBreaks against attacks from untrustworthy networks, called RedNets. All incoming transactions from the RedNet are examined by the FireBreak to determine if they violate any of a plurality of protection rules stored in a local protection rules database. Any transaction found to be in violation is discarded. Valid transactions are forwarded to the BlackNet. If an otherwise valid transaction is found to be suspicious, the FireBreak will forward to a FireNet Server relevant information relating to that transaction. If the FireNet Server verifies that the transaction is indeed part of an attack, the FireNet Server will create new protection rules suitable to defend against the newly identified source or strategy of attack. Periodically, all FireBreaks in the FireNet system will transfer, directly or indirectly, all new rules.