Jeffrey W Perkins

US Patent:

6675339, Jan 6, 2004

Filed:

Aug 22, 2001

Appl. No.:

09/935453

Inventors:

Kenneth J. Lanier - Medway MA
Roger W. Blethen - Dover MA
H. Neil Kelly - Westwood MA
Michael G. Davis - San Jose CA
Jeffrey H. Perkins - Cambridge MA
Tommie Berry - Pleasanton CA
Phillip Burlison - Morgan Hill CA
Mark Deome - San Jose CA
Christopher J. Hannaford - South Weymouth MA
Edward J. Terrenzi - Walpole MA
David Menis - Cohasset MA
David W. Curry - Cohasset MA
Eric Rosenfeld - Ashland MA

Assignee:

LTX Corporation - Westwood MA

International Classification:

G01R 3128

US Classification:

714744, 714798

Abstract:

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals.

US Patent:

7092837, Aug 15, 2006

Filed:

Sep 15, 2003

Appl. No.:

10/663469

Inventors:

Kenneth J. Lanier - Medway MA, US
Roger W. Blethen - Dover MA, US
H. Neil Kelly - Westwood MA, US
Michael G. Davis - San Jose CA, US
Jeffrey H. Perkins - Cambridge MA, US
Tommie Berry - Pleasanton CA, US
Phillip Burlison - Morgan Hill CA, US
Mark Deome - San Jose CA, US
Christopher J. Hannaford - South Weymouth MA, US
Edward J. Terrenzi - Walpole MA, US
David Menis - Cohasset MA, US
David W. Curry - Cohasset MA, US
Eric Rosenfeld - Ashland MA, US

Assignee:

LTX Corporation - Westwood MA

International Classification:

G06F 1/06

US Classification:

702117, 702110, 702118, 702121

Abstract:

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals.