Jeffrey D Pickholtz

US Patent:

8278692, Oct 2, 2012

Filed:

Oct 22, 2009

Appl. No.:

12/589331

Inventors:

Vinod J. Ambrose - Northborough MA, US
Jeffrey D. Pickholtz - Marlborough MA, US
Randy L. Allmon - North Grafton MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/78

US Classification:

257288, 257297, 257E29255

Abstract:

In some embodiments, complementary charge-collecting diffusions (transistor diffusions, e. g. , drain or source areas) are disposed close to each other. In some embodiments, dummy (“off”) transistors are incorporated to bring complementary diffusions (diffusions of the same charge type and having complementary digital logic levels) closer to each other than otherwise might be possible and thus, to enhance common-mode charge collection for the complementary diffusion areas.

US Patent:

6463548, Oct 8, 2002

Filed:

May 10, 1999

Appl. No.:

09/309070

Inventors:

Daniel W. Bailey - Northborough MA
Jeffrey D. Pickholtz - Marlboro MA
Shane L. Bell - Shrewsbury MA

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F 104

US Classification:

713503, 713600

Abstract:

A method and apparatus are provided for ensuring that a clocked circuit will function after fabrication, regardless of the presence of clock skew. More particularly, a method and apparatus are shown for de-skewing the clock signals of such a clocked circuit only when clock skew is present. When such clock skew does not develop, peak performance of the associated circuit can be achieved by turning off the de-skewing function without removing that functionality from the circuit.

US Patent:

6463547, Oct 8, 2002

Filed:

Dec 8, 1999

Appl. No.:

09/457604

Inventors:

Daniel W. Bailey - Northboro MA
Jeffrey D. Pickholtz - Marlboro MA
Shane L. Bell - Shrewsbury MA
William J. Bowhill - Framingham MA

Assignee:

Compaq Information Technologies Group LP - Houston TX

International Classification:

G06F 104

US Classification:

713500, 713503

Abstract:

A clock distribution system for a semiconductor device provides for both on-chip and in-package clock distribution via on-chip and in-package clock distribution networks. Each of these networks is selectively enabled depending on the mode of operation. Specifically, for wafer testing, the on-chip clock distribution network is selected. Thus, a probe tester need only provide a single clock source with conventional timing specifications to test the operation of the chip. In contrast, during normal operation, an in-package clock distribution network is enabled. In-package clock routing provides the lowest variation mode and thus, will result in the maximum clock frequency for the chip.