Jeffrey M Price

US Patent:

6658478, Dec 2, 2003

Filed:

Aug 4, 2000

Appl. No.:

09/633088

Inventors:

Ashok Singhal - Redwood City CA
Jeffrey A. Price - Pleasanton CA
David J. Broniarczyk - Mountain View CA
George C. Cameron - Capitola CA

Assignee:

3PARdata, Inc. - Fremont CA

International Classification:

G06F 1516

US Classification:

709232, 709239, 710 38, 710316

Abstract:

A data storage system includes a plurality of nodes for providing access to a data storage facility. Each node has a computer-memory complex to provide general purpose computing for the node, a node controller to control data transfers through the respective node, and a cluster memory to buffer data for the data transfers. A plurality of communication paths interconnect the nodes, with a separate communication path provided for each two nodes of the data storage system.

US Patent:

7120179, Oct 10, 2006

Filed:

Nov 6, 2003

Appl. No.:

10/703698

Inventors:

Robert L. Fennelly - San Jose CA, US
Andreas Weber - Los Altos CA, US
Jeffrey Bryant Price - Sunnyvale CA, US
Stephan C. Burdick - Cupertino CA, US
Gregory D. Woods - Belmont CA, US
Greta L. Light - San Mateo CA, US

Assignee:

Finisar Corporation - Sunnyvale CA

International Classification:

H01S 3/00

US Classification:

372 3802, 372 3807

Abstract:

An apparatus and method are provided for setting the AC and DC bias levels of a laser diode in an optoelectronic transceiver so as to control the device's extinction ratio. An optical output of the transceiver is looped back to an optical input of the transceiver. The method includes setting a DC bias level for the laser diode, setting an AC bias level for the laser diode to each of a predefined sequence of AC bias level settings, and receiving from the transceiver a sequence of optical output power measurements, the sequence of optical output power measurements including an average optical output power measurement corresponding to each of the AC bias level settings in the predefined sequence. From the received sequence of optical output power measurements preferred AC and DC bias level settings are determined and stored in the transceiver so as to control the AC and DC bias levels of the laser diode.

US Patent:

7155133, Dec 26, 2006

Filed:

Mar 18, 2002

Appl. No.:

10/101258

Inventors:

James Stewart - San Jose CA, US
Anthony Ho - Sunnyvale CA, US
Rudolf J. Hofmeister - Sunnyvale CA, US
Darin James Douma - Monrovia CA, US
Lucy G. Hosking - Santa Cruz CA, US
Andreas Weber - Los Altos CA, US
Jeffrey Bryant Price - Sunnyvale CA, US

Assignee:

Finisar Corporation - Sunnyvale CA

International Classification:

H04B 10/06

US Classification:

398202, 250214 R, 250214 SW

Abstract:

A controller for controlling the reverse-bias voltage of an avalanche photodiode in a transceiver or receiver. The controller includes memory for storing information related to the avalanche photodiode, and analog to digital conversion circuitry for receiving an analog signal corresponding to the temperature of the avalanche photodiode, converting the received analog signal into a digital value, and storing the digital value in a predefined location within the memory. Control circuitry in the controller controls the operation of the avalanche photodiode and a temperature lookup table store in the memory. A serial interface enables a host device to read from and write to locations within the memory. The invention also controls the reverse-bias voltage of an avalanche photodiode in a transceiver or receiver.

US Patent:

7217914, May 15, 2007

Filed:

Jul 27, 2004

Appl. No.:

10/899904

Inventors:

James Stewart - San Jose CA, US
Anthony Ho - Sunnyvale CA, US
Rudolf J. Hofmeister - Sunnyvale CA, US
Darin James Douma - Monrovia CA, US
Lucy G. Hosking - Santa Cruz CA, US
Andreas Weber - Los Altos CA, US
Jeffrey Bryant Price - Sunnyvale CA, US

Assignee:

Finisar Corporation - Sunnyvale CA

International Classification:

H01J 40/14
H01L 35/00
H02H 5/04

US Classification:

250214R, 327513, 361 938

Abstract:

Methods and processes are disclosed for calibrating optoelectronic devices, such as optoelectronic transceivers and optoelectronic receivers, based upon an avalanche photodiode breakdown voltage. In general, the method involves adjusting a reverse-bias voltage of the avalanche photodiode until avalanche breakdown of the avalanche photodiode occurs. An optimized APD reverse-bias voltage is then determined by reducing the reverse-bias voltage at which avalanche breakdown occurs by a predetermined offset voltage. This process is performed at a variety of different temperatures. Information concerning each temperature and the corresponding optimized APD reverse-bias voltage is stored in a memory of the optoelectronic device.

US Patent:

7543100, Jun 2, 2009

Filed:

Jun 18, 2001

Appl. No.:

09/883681

Inventors:

Ashok Singhal - Redwood City CA, US
Jeffrey A. Price - Pleasanton CA, US
David J. Broniarczyk - Mountain View CA, US
George R. Cameron - Capitola CA, US

Assignee:

3PAR, Inc. - Fremont CA

International Classification:

G06F 13/14

US Classification:

710305, 710100, 710300, 711112, 711113, 711114, 709211

Abstract:

A node controller for a data storage system having at least one node provides access to a data storage facility. The node controller is distinct from a computer-memory complex of the node. The node controller provides overall control for transferring data through the node.

US Patent:

20050001152, Jan 6, 2005

Filed:

Jul 27, 2004

Appl. No.:

10/899941

Inventors:

James Stewart - San Jose CA, US
Anthony Ho - Richmond CA, US
Rudolf Hofmeister - Sunnyvale CA, US
Darin Douma - Monrovia CA, US
Stephen Hosking - Santa Cruz CA, US
Andreas Weber - Los Altos CA, US
Jeffrey Price - Sunnyvale CA, US

International Classification:

H01J040/14

US Classification:

25021400R

Abstract:

Methods and processes are disclosed for calibrating optoelectronic devices, such as optoelectronic transceivers and optoelectronic receivers, based upon a measured avalanche photodiode bit error rate. In general, the method involves measuring a bit error rate for the avalanche photodiode and adjusting the reverse bias voltage of the avalanche photodiode until the bit error rate is minimized. This process is repeated for each of a variety of different thermal conditions. Information concerning each thermal condition and the corresponding reverse bias voltage is stored in a memory of the optoelectronic device.

US Patent:

20130042066, Feb 14, 2013

Filed:

Jun 8, 2011

Appl. No.:

13/642045

Inventors:

Jeffrey A. Price - Pleasanton CA, US

International Classification:

G06F 12/08

US Classification:

711119, 711118, 711E12017, 711E12023

Abstract:

The present disclosure provides a method for processing a storage operation in a system with an added level of storage caching. The method includes receiving, in a storage cache, a read request from a host processor that identifies requested data and determining whether the requested data is in a cache memory of the storage cache. If the requested data is in the cache memory of the storage cache, the requested data may be obtained from the storage cache and sent to the host processor. If the requested data is not in the cache memory of the storage cache, the read request may be sent to a host bus adapter operatively coupled to a storage system. The storage cache is transparent to the host processor and the host bus adapter.

US Patent:

20160062897, Mar 3, 2016

Filed:

Oct 15, 2015

Appl. No.:

14/884188

Inventors:

- Houston TX, US
Jeffrey A. Price - Pleasanton CA, US

International Classification:

G06F 12/08

Abstract:

The present disclosure provides a method for processing a storage operation in a system with an added level of storage caching. The method includes receiving, in a storage cache, a read request from a host processor that identifies requested data and determining whether the requested data is in a cache memory of the storage cache. If the requested data is in the cache memory of the storage cache, the requested data may be obtained from the storage cache and sent to the host processor. If the requested data is not in the cache memory of the storage cache, the read request may be sent to a host bus adapter operatively coupled to a storage system. The storage cache is transparent to the host processor and the host bus adapter.