Jeffrey J Rooney

Address:

152 102 Ln NE, Minneapolis, MN 55434

Phone:

7637840569

VIN:

1NXBR32E47Z868591

Make:

TOYOTA

Model:

COROLLA

Year:

2007

US Patent:

6385680, May 7, 2002

Filed:

Oct 15, 1999

Appl. No.:

09/418468

Inventors:

Douglas A. Larson - Lakeville MN
Joseph Jeddeloh - Blaine MN
Jeffrey J. Rooney - Blaine MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1300

US Classification:

710119, 710107, 710244, 710240

Abstract:

One embodiment of the present invention provides a method for flexibly allocating I/O pins used for bus grant signals between bus controllers located on a semiconductor chip. The method operates by receiving a first set of grant lines from a first bus arbitration circuit. This first set of grant lines is used to grant control of a first bus to devices on the first bus. The method divides the first set of grant lines into a first subset of grant lines and a second subset of grant lines. The method also receives a second set of grant lines from a second bus arbitration circuit. This second set of grant lines is used to grant control of a second bus to devices on the second bus. The method divides the second set of grant lines into a third subset of grant lines and a fourth subset of grant lines. Next, the method selects outputs from between the first subset of grant lines and the third subset of grant lines, and drives the outputs off of the semiconductor chip through a first set of output pins. During a first mode of operation, the first subset of grant lines is selected to be driven through the first set of output pins, and during a second mode of operation the third subset of grant lines is selected to driven through the first set of output pins.

US Patent:

6389492, May 14, 2002

Filed:

Oct 15, 1999

Appl. No.:

09/418465

Inventors:

Douglas A. Larson - Lakeville MN
Joseph Jeddeloh - NE. Blaine MN
Jeffrey J. Rooney - Blaine MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1300

US Classification:

710107, 710240, 710 52

Abstract:

One embodiment of the present invention provides an apparatus that flexibly allocates I/O pins used for bus grant signals between bus controllers. The apparatus includes a semiconductor chip containing a first bus arbitration circuit and a second bus arbitration circuit. A first set of grant lines originates from the first bus arbitration circuit and is used to grant control of a first bus to devices on the first bus. This first set of grant lines is divided into a first subset of grant lines and a second subset of grant lines. A second set of grant lines originates from the second bus arbitration circuit and is used to grant control of a second bus to devices on the second bus. This second set of grant lines is divided into a third subset of grant lines and a fourth subset of grant lines. A selector circuit selects a plurality of outputs from between the first subset of grant lines and the third subset of grant lines. This plurality of outputs is coupled to a first set of output pins on the semiconductor chip.

US Patent:

6601118, Jul 29, 2003

Filed:

Jun 6, 2000

Appl. No.:

09/589043

Inventors:

Jeffrey Jay Rooney - Red Wing MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1202

US Classification:

710 56, 710 22, 710 52, 710 53, 710100, 710101, 710128, 711 1, 711117

Abstract:

A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to control data flow between the processor and the computer bus. The dynamic buffer allocation system allows simultaneous data transfer from the processor to the buffers, and from the buffers to the computer bus.

US Patent:

7590764, Sep 15, 2009

Filed:

Jul 29, 2003

Appl. No.:

10/630635

Inventors:

Jeffrey Jay Rooney - Red Wing MN, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 13/38

US Classification:

710 5, 710 6, 710 19, 710 56, 710309, 710310

Abstract:

A system for dynamically allocating buffers between components in a computer system is described. The system uses matched sets of bi-directional buffers to control data flow between the processor and the computer bus. The dynamic buffer allocation system allows simultaneous data transfer from the processor to the buffers, and from the buffers to the computer bus.

US Patent:

7694202, Apr 6, 2010

Filed:

Jan 28, 2004

Appl. No.:

10/766611

Inventors:

Travis E. Swanson - Ramsey MN, US
Jeffrey J. Rooney - Blaine MN, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 31/28
G06F 7/02

US Classification:

714738, 714739, 714821

Abstract:

A system and method to provide memory test patterns for the calibration of a delay locked loop (DLL) using a pseudo random bit sequence (PRBS) stored in a serial presence detect (SPD) circuit memory. The test bits stored in the SPD memory are transferred to a memory controller register (MCR) and implemented on the system data bus as test patterns that closely simulate run-time switching conditions on the system bus, so as to allow more accurate calibration of the DLL. Test data write/read operations may be performed while signals for the test patterns are present on various bit lines in the data bus so as to allow for accurate determination or adjustment of the value for the delay to be provided by the DLL to the strobe signals during memory data reading operations at run time. Memory chips may also be tested over an operating range of values using the generated test patterns.

US Patent:

7707473, Apr 27, 2010

Filed:

Aug 2, 2006

Appl. No.:

11/497849

Inventors:

Paul A. LaBerge - Shoreview MN, US
Jeffrey J. Rooney - Blaine MN, US
Charles K. Snodgrass - Bosie ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 11/00
G11C 29/00
G01R 31/02
G01R 31/26

US Classification:

714738, 714723, 714704, 324763, 324765

Abstract:

Embodiments herein may enable an algorithmic pattern generator (APG) to present iterative values of one or more operational parameters to a device under test (DUT). At each iteration, one or more test patterns may be presented to the DUT. The APG may capture test results from a set of iterations of the operational parameters. The APG may also write values associated with a next operational parameter to be iterated to a test parameter configuration space within the device tester.

US Patent:

7944234, May 17, 2011

Filed:

Mar 19, 2008

Appl. No.:

12/051723

Inventors:

Kirsten S. Lunzer - Arden Hills MN, US
Jeffrey J. Rooney - Blaine MN, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H03K 19/173

US Classification:

326 38, 326 41, 326 47, 714 30, 714 31, 714 39

Abstract:

Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to transition to a programmable state at a programmable number of occurrences of a programmable set of events associated with a first subset of signals on a first subset of input signal paths. States associated with a second subset of signals on a second subset of input signal paths may be stored at a time relative to a transition to the programmable state if a set of storage criteria have been met. Additional embodiments are disclosed and claimed.

US Patent:

8575958, Nov 5, 2013

Filed:

May 13, 2011

Appl. No.:

13/107580

Inventors:

Kirsten S. Lunzer - Arden Hills MN, US
Jeffrey J. Rooney - Blaine MN, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H03K 19/173

US Classification:

326 38, 326 41, 326 47, 326 54, 326104, 714 31, 714 39

Abstract:

Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to transition to a programmable state at a programmable number of occurrences of a programmable set of events associated with a first subset of signals on a first subset of input signal paths. States associated with a second subset of signals on a second subset of input signal paths may be stored at a time relative to a transition to the programmable state if a set of storage criteria have been met. Additional embodiments are disclosed and claimed.