Jeffrey D Sanders

US Patent:

7245191, Jul 17, 2007

Filed:

Sep 1, 2005

Appl. No.:

11/217183

Inventors:

Jeffrey Sanders - Thousand Oaks CA, US

Assignee:

Inphi Corporation - Westlake Village CA

International Classification:

H03B 5/12
H03L 7/00

US Classification:

331179, 331 16, 331 17, 331 34, 331 44

Abstract:

A PLL circuit provides a self-selecting divide ratio, which is varied as necessary to lock the circuit to a reference clock which may have several possible frequencies, thereby enabling the VCO to employ a type of oscillator having a superior jitter characteristic. The PLL circuit includes a variable divider which divides the VCO output by a divide ratio value provided by a frequency band select circuit, which provides the divide ratio needed to drive the phase difference between the reference and divided clocks toward zero while the VCO clock output operates within a predetermined frequency range. The self-selecting variable divide ratio allows the VCO's oscillator to have a narrow output frequency range, thereby allowing the use of an oscillator type with a jitter characteristic which may be low enough to meet the requirements of JEDEC, for example.

US Patent:

20160006441, Jan 7, 2016

Filed:

Jul 2, 2014

Appl. No.:

14/322375

Inventors:

- North Reading MA, US
Jeffrey Wade Sanders - Thousand Oaks CA, US
Thomas Aquinas Repucci - Blaine MN, US
Ronald A. Sartschev - Andover MA, US

Assignee:

Teradyne, Inc. - North Reading MA

International Classification:

H03L 7/08
H03K 5/14
H03L 7/099

Abstract:

An automatic test system configured for generating a periodic signal of a programmable frequency. The automatic test system may comprise a clock, an edge generator coupled to the clock, a phase locked loop, and a delay adjustment circuit. The edge generator may comprise an edge generator output, an enable input and a delay input. The edge generator may produce at the edge generator output a signal with a delay relative to an edge of the clock specified by a value at the delay input in each cycle of the clock for which the enable input is asserted. The phase locked loop may comprise a reference input and a phase locked loop output configured to provide the periodic signal of the programmable frequency. The delay adjustment circuit may comprise an accumulator that may increase in value by a programmed amount for each cycle of the clock.