Jeffrey C Shearer

US Patent:

20220406776, Dec 22, 2022

Filed:

Jun 21, 2021

Appl. No.:

17/304392

Inventors:

- ARMONK NY, US
Eric Miller - Watervliet NY, US
Dechao Guo - Niskayuna NY, US
Jeffrey C. Shearer - Albany NY, US
Su Chen Fan - Cohoes NY, US
Julien Frougier - Albany NY, US
Veeraraghavan S. Basker - Schenectady NY, US
Junli Wang - Slingerlands NY, US
Sung Dae Suk - Watervliet NY, US

International Classification:

H01L 27/092
H01L 29/04
H01L 29/06
H01L 29/423
H01L 29/786
H01L 21/02
H01L 21/8238
H01L 29/66

Abstract:

A semiconductor device comprising at least one first gate all around channel having a horizontal physical orientation, wherein the at least one first gate all around channel is comprised of a first material, wherein the at least one first gate all around channel has a sidewall surface with (100) crystal orientation. At least one second gate all around channel having a vertical physical orientation, wherein the second channel is located above the at least one first gate all around channel, wherein the at least one second gate all around channel is comprised of a second material, wherein the at least one second gate all around channel has a sidewall surface with (110) crystal orientation. A gate metal enclosing the at least one first gate all around channel and the at least one second gate all around channel.

US Patent:

20220199785, Jun 23, 2022

Filed:

Dec 17, 2020

Appl. No.:

17/125775

Inventors:

- Armonk NY, US
Eric Miller - Watervliet NY, US
Jeffrey C. Shearer - Albany NY, US
Su Chen Fan - Cohoes NY, US
Heng Wu - Guilderland NY, US

International Classification:

H01L 29/40
H01L 29/417
H01L 29/08
H01L 29/66
H01L 29/78

Abstract:

A semiconductor structure and a method of making the same includes a first recessed region in a semiconductor structure, the first recessed region defining a first opening with a first positive tapering profile, as at least part of the first positive tapering profile, widening the first opening in a direction towards a top source/drain region of the semiconductor structure at a first tapering angle, and a top source/drain contact within the first opening, the top source/drain contact surrounding a surface of the top source/drain region. The semiconductor structure further includes a protective liner located at an interface between a bottom portion of the top source/drain region, a top spacer adjacent to the top source/drain region and a dielectric material between two consecutive top source/drain regions, the protective liner protects the top source/drain regions during contact patterning.

US Patent:

20200243648, Jul 30, 2020

Filed:

Feb 21, 2020

Appl. No.:

16/798240

Inventors:

- San Jose CA, US
Siva Kanakasabapathy - Pleasanton CA, US
Andrew M. Greene - Albany NY, US
Jeffrey Shearer - Albany NY, US
Nicole A. Saulnier - Albany NY, US

Assignee:

TESSERA, INC. - San Jose CA

International Classification:

H01L 29/10
H01L 21/8234
H01L 21/8238
H01L 29/66
H01L 27/088
H01L 29/78
H01L 27/092
H01L 21/02
H01L 25/065
H01L 29/417

Abstract:

Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.

US Patent:

20200090998, Mar 19, 2020

Filed:

Nov 20, 2019

Appl. No.:

16/689621

Inventors:

- Armonk NY, US
Marc Bergendahl - Rensselaer NY, US
Victor W. C. Chan - Guilderland NY, US
JEFFREY C. SHEARER - ALBANY NY, US

International Classification:

H01L 21/768
H01L 21/027
H01L 21/311
H01L 21/8238

Abstract:

According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.

US Patent:

20200006137, Jan 2, 2020

Filed:

Jun 27, 2018

Appl. No.:

16/020412

Inventors:

- Armonk NY, US
Marc Bergendahl - Rensselaer NY, US
Victor W. C. Chan - Guilderland NY, US
JEFFREY C. SHEARER - ALBANY NY, US

International Classification:

H01L 21/768
H01L 21/8238
H01L 21/027
H01L 21/311

Abstract:

According to embodiments of the present invention, a method of forming a self-aligned contact includes depositing an etch-stop liner on a surface of a gate cap and a contact region. A dielectric oxide layer is deposited onto the etch-stop layer. The dielectric oxide layer and the etch-stop liner are removed in a region above the contact region to form a removed region. A contact is deposited in the etched region.

US Patent:

20190189517, Jun 20, 2019

Filed:

Jan 10, 2019

Appl. No.:

16/244493

Inventors:

- Armonk NY, US
Siva Kanakasabapathy - Pleasanton CA, US
Andrew M. Greene - Albany NY, US
Jeffrey Shearer - Albany NY, US
Nicole A. Saulnier - Albany NY, US

International Classification:

H01L 21/8234
H01L 21/8238
H01L 29/78
H01L 29/66
H01L 25/065
H01L 21/02
H01L 27/088

Abstract:

Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.

US Patent:

20190164773, May 30, 2019

Filed:

Nov 28, 2017

Appl. No.:

15/824175

Inventors:

- Armonk NY, US
Robert L. Bruce - White Plains NY, US
Sebastian U. Engelmann - White Plains NY, US
Nathan P. Marchack - New York NY, US
Hiroyuki Miyazoe - White Plains NY, US
Jeffrey C. Shearer - ALBANY NY, US
Takefumi Suzuki - Tokyo, JP

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/311
H01L 21/768

Abstract:

A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.

US Patent:

20190157140, May 23, 2019

Filed:

Jan 2, 2019

Appl. No.:

16/237886

Inventors:

- Armonk NY, US
Jessica Dechene - Watervliet NY, US
Susan S. Fan - Cohoes NY, US
Son V. Nguyen - Schenectady NY, US
Jeffrey C. Shearer - Albany NY, US

International Classification:

H01L 21/768
H01L 23/532
H01L 23/522
H01L 27/088

Abstract:

An upper layer is formed in a first interlayer dielectric (ILD) layer. The upper layer comprises a plurality of metal interconnects and one or more upper layer air gaps positioned between adjacent metal interconnects. A lower layer is formed in the first ILD layer. The lower layer comprises one or more vias, and one or more lower air gaps positioned between adjacent vias. The upper layer and the lower layer are formed in accordance with a dual-damascene process.