Jeffrey R Stevens

US Patent:

6505260, Jan 7, 2003

Filed:

Feb 15, 2001

Appl. No.:

09/784690

Inventors:

Kenneth T. Chin - Cypress TX
C. Kevin Coffee - Pembroke Pines FL
Michael J. Collins - Pleasonton CA
Jerome J. Johnson - Spring TX
Phillip M. Jones - Spring TX
Robert A. Lester - Houston TX
Gary J. Piccirillo - Cypress TX
Jeffrey C. Stevens - Spring TX

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F 1318

US Classification:

710 41, 710 42, 711151

Abstract:

A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming âmemory-starved. â Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.

US Patent:

6601168, Jul 29, 2003

Filed:

Nov 19, 1999

Appl. No.:

09/443575

Inventors:

Charles J. Stancil - Tomball TX
Jeffrey C. Stevens - Spring TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 900

US Classification:

713100, 713300

Abstract:

A fan speed controller for a computer system that calculates an internal central processing unit temperature and, in response to target fan speeds communicated over a system management bus, slowly adjusts the computer system fan speed such that audible noise associated with the fan speed change is not as perceptible as would be an immediate change in fan speed.

US Patent:

20020097220, Jul 25, 2002

Filed:

Mar 28, 2002

Appl. No.:

10/109134

Inventors:

Patrick Ferguson - Cypress TX, US
Jeffrey Stevens - Spring TX, US

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G09G005/00

US Classification:

345/156000

Abstract:

A computer interface extension configuration that includes a host having a motherboard, an extension transmitter card, and an extension receiver. The motherboard includes a first connector that allows motherboard signals to be shared internal to the host, and a second connector separate from the first connector that supports communications with the host. The extension transmitter card is positioned within the host and is electrically connected to the motherboard of the host via at least the first connector and the second connector. The extension transmitter card has an audio controller that interfaces with the second connector independent from communications that occur on the first connector. The extension receiver is connected to a plurality of user interface devices and is extensibly connected to the extension transmitter card. The extension receiver, among other things, receives data transmissions from the extension transmitter card of the host to thereby provide the data transmissions to one or more of the plurality of user interface devices. The audio controller of the extension transmitter card interfaces with audio communications of the extension receiver.

US Patent:

20030126323, Jul 3, 2003

Filed:

Dec 31, 2001

Appl. No.:

10/035778

Inventors:

Patrick Ferguson - Cypress TX, US
Jeffrey Stevens - Spring TX, US

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F013/12

US Classification:

710/063000

Abstract:

A computer interface extension configuration that includes a host having a motherboard, an extension transmitter card, and an extension receiver. The motherboard includes a first connector that allows motherboard signals to be shared internal to the host, and a second connector separate from the first connector that supports communications with the host. The extension transmitter card is positioned within the host and is electrically connected to the motherboard of the host via at least the first connector and the second connector. The extension transmitter card has a graphics controller that interfaces with the second connector independent from communications that occur on the first connector. The extension receiver is connected to a plurality of user interface devices and extensibly connected to the extension transmitter card. The extension receiver, among other things, receives data transmissions from the extension transmitter card of the host to thereby provide the data transmissions to one or more of the plurality of user interface devices.

US Patent:

56175574, Apr 1, 1997

Filed:

Nov 14, 1994

Appl. No.:

8/339086

Inventors:

Jeffrey C. Stevens - Spring TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1216

US Classification:

395473

Abstract:

A circuit for responding to a microprocessor-generated write of a write-protected area of memory by invalidating a cache line corresponding to a write address in a microprocessor's internal cache by using a microprocessor address pin as a snoop invalidate signal during snoop cycles. This allows write-protected areas of a main memory to be cached in the internal cache of the microprocessor. The circuit monitors a processor bus to determine if the address associated with a write cycle corresponds to the write-protected area of memory. If so, the circuit latches in the write address, gains control of the processor bus by asserting an address hold signal to float the address pins of the microprocessor, and generates a snoop cycle on the processor bus. The cache line of the microprocessor's internal cache corresponding to the snoop address is invalidated, thereby preserving coherency of the write-protected data.

US Patent:

60414014, Mar 21, 2000

Filed:

Feb 27, 1998

Appl. No.:

9/032429

Inventors:

Jens K. Ramsey - Houston TX
Jeffrey C. Stevens - Spring TX
Michael E. Tubbs - Montgomery TX
Charles J. Stancil - Tomball TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1200

US Classification:

712 43

Abstract:

A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs).

US Patent:

54468639, Aug 29, 1995

Filed:

Dec 16, 1993

Appl. No.:

8/168718

Inventors:

Jeffrey C. Stevens - Spring TX
Jens K. Ramsey - Houston TX
Randy M. Bonella - Cypress TX
Philip C. Kelly - Houston TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1212

US Classification:

395427

Abstract:

A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i. e.

US Patent:

53353358, Aug 2, 1994

Filed:

Aug 30, 1991

Appl. No.:

7/753420

Inventors:

Mike T. Jackson - Houston TX
Jeffrey C. Stevens - Spring TX
Roger E. Tipley - Houston TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1200

US Classification:

395425

Abstract:

A method and apparatus for enabling a dual ported cache system in a multiprocessor system to guarantee snoop access to all host bus cycles which require snooping. The cache controller includes a set of latches coupled to the host bus which it uses to latch the state of the host bus during a snoop cycle if the cache controller is unable to immediately snoop that cycle. The cache controller latches that state of the host bus in the beginning of a cycle and preserves this state throughout the cycle due to the effects of pipelining on the host bus. In addition, the cache controller is able to delay host bus cycles to guarantee snoop access to host bus cycles which require snooping. The cache controller generally only delays a host bus cycle when it is already performing other tasks, such as servicing its local processor, and cannot snoop the host bus cycle immediately. When the cache controller latches the state of the bus during a write cycle, it only begins to delay the host bus after a subsequent cycle begins. In this manner, one write cycle can complete on the host bus before the cache controller delays any cycles, thereby reducing the impact of snooping on host bus bandwidth.