Jeffrey Howard Summers

US Patent:

8635621, Jan 21, 2014

Filed:

Aug 22, 2008

Appl. No.:

12/187351

Inventors:

David Stephen Levitan - Austin TX, US
Jeffrey Richard Summers - Raleigh NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30
G06F 9/46

US Classification:

718103, 718102, 718104, 712208, 712214

Abstract:

The invention relates to a method and apparatus for execution scheduling of a program thread of an application program and executing the scheduled program thread on a data processing system. The method includes: providing an application program thread priority to a thread execution scheduler; selecting for execution the program thread from a plurality of program threads inserted into the thread execution queue, wherein the program thread is selected for execution using a round-robin selection scheme, and wherein the round-robin selection scheme selects the program thread based on an execution priority associated with the program thread bit; placing the program thread in a data processing execution queue within the data processing system; and removing the program thread from the thread execution queue after a successful execution of the program thread by the data processing system.

US Patent:

20100262813, Oct 14, 2010

Filed:

Apr 14, 2009

Appl. No.:

12/423608

Inventors:

Mary D. Brown - Austin TX, US
Richard W. Doing - Raleigh NC, US
Kevin N. Magill - Raleigh NC, US
Brian R. Mestan - Austin TX, US
Wolfram M. Sauer - Austin TX, US
Balaram Sinharoy - Poughkeepsie NY, US
Jeffrey R. Summers - Raleigh NC, US
Albert J. Van Norstrand, JR. - Round Rock TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/38

US Classification:

712240, 712234, 712E09045

Abstract:

Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.