Jeffrey L Swanson

US Patent:

6587965, Jul 1, 2003

Filed:

Apr 29, 2000

Appl. No.:

09/563004

Inventors:

Ian P. Shaeffer - San Jose CA
Jeffrey C. Swanson - Sunnyvale CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1100

US Classification:

714 28, 703 28

Abstract:

The present invention provides for a method and system for external observation of a dual mode control interface, via a single point of entry/exit from a chip. In operation, data is sent into and retrieved from a chip using a single point on the chip. Multiple test methods can be used with the proper test method selected by an established hierarchy of methods. In one embodiment, an impedance is shown for control purposes between test methods.

US Patent:

6591332, Jul 8, 2003

Filed:

Apr 28, 2000

Appl. No.:

09/561332

Inventors:

Jeffrey C. Swanson - Sunnyvale CA
John A. Wickeraad - Granite Bay CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1200

US Classification:

711108, 711144, 711145, 711122

Abstract:

An apparatus and method using a valid bit in a cache entry address first-in-first-out (FIFO) to indicate when a cache entry can be flushed in a coherent memory domain. One embodiment of the invention involves a method for tracking a cache entry in a cache serving data transfers between a coherent memory domain and a non-coherent memory domain in a data processing system, including steps of storing an address corresponding to a cache entry in a FIFO register, using at least one register cell as a valid flag to indicate when the cache entry is still in the cache, and changing the valid flag based on one or more signals transmitted from the non-coherent memory domain. A second embodiment of the invention involves a data processing system or an I/O bridge host, having a cache and multiple cache entries, serving data transfers between a coherent memory domain and a non-coherent memory domain, including registers configured to store an address corresponding to a cache entry, wherein each FIFO register has a valid flag to indicate when the cache entry is still in the cache, and the valid flag can be changed based on one or more signals transmitted from the non-coherent memory domain.

US Patent:

6594714, Jul 15, 2003

Filed:

May 1, 2000

Appl. No.:

09/561953

Inventors:

Jeffrey C. Swanson - Sunnyvale CA
Debendra Das Sharma - Santa Clara CA
Jason Jones - Oxnard CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 300

US Classification:

710 51, 710 38, 710 36

Abstract:

A reconfigurable register array structure allows an agent to transmit data from a single channel or in bundled form from multiple channels. The structure makes economical use of valuable chip space by reducing the size of the overall register array system. A coalescing prestage is used to collect data from single channels or from multiple channels and to multiplex the data, based on a priority scheme, to supply the data to a primary stage of first-in-first-out register arrays. The coalescing prestage may include one or more first registers, a delay register, multiplexers to select outputs of the first registers, and multiplexers to select outputs of the delay register. Alternatively, the coalescing prestage may include one or more register array structures, each such structure having independent write ports, one for each channel. Data coalesced in the coalescing prestage is provided to a primary stage. The primary stage may include one or more logical register arrays configured as one physical array.

US Patent:

6662313, Dec 9, 2003

Filed:

Apr 29, 2000

Appl. No.:

09/563059

Inventors:

Jeffrey C. Swanson - Sunnyvale CA
Sharon M. Ebner - Mountain View CA
John A. Wickeraad - Granite Bay CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1100

US Classification:

714 39, 714 30, 714 31

Abstract:

Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A test device includes a state machine responsive to (i) an arm command for transitioning from a standby state to an armed state, (ii) a final trigger event for transitioning from the armed state to a triggered state, and (iii) a post trigger count event for transitioning from the triggered state to the standby state. A controller provides the arm command and issues appropriate configuration controls to collect signal samples. In particular, a network responds to these commands from the controller to selectively provide signal samples from a device under test. A trigger event generator responds to logic or other characteristics of the signal samples to provide trigger events. These trigger events are counted by a trigger event counter in the armed state of the state machine to identify the final trigger event corresponding to an occurrence of a programmable number of the trigger events.

US Patent:

6775640, Aug 10, 2004

Filed:

Apr 28, 2000

Appl. No.:

09/560189

Inventors:

Jeffrey C. Swanson - Sunnyvale CA
John A. Wickeraad - Granite Bay CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 742

US Classification:

702182, 702189

Abstract:

A performance adder for providing a running total of performance values within an integrated circuit chip. The performance adder is triggered by various performance events as determined through multiplexer logic for detecting occurrence of a particular performance event. The multiplexer logic can also trigger the performance adder through atomic, edge, toggle, or on/off signals related to the performance events or through a logical function of a combination of performance events. The performance adders can be used to compute average latency of a component in the circuit.

US Patent:

7117297, Oct 3, 2006

Filed:

May 23, 2003

Appl. No.:

10/443747

Inventors:

Jeffrey Charles Swanson - Sunnyvale CA, US
Debendra Das Sharma - Santa Clara CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/00

US Classification:

711104, 711110, 711169

Abstract:

A method and apparatus for storing and reading an entry having one of a plurality of entry types and storing order information about stored entries, using a single addressable storage array. An index pipe maintains first in, first out order of the entries stored in the addressable storage array. Stages in the index pipe store a value representing the address of the stored entry in the storage array, the type of the stored entry, and the validity of the stored entry. Additional control logic implements order rules between entry types.

US Patent:

7325164, Jan 29, 2008

Filed:

Sep 25, 2003

Appl. No.:

10/670620

Inventors:

Jeffrey C. Swanson - Sunnyvale CA, US
Sharon M. Ebner - Mountain View CA, US
John A. Wickeraad - Granite Bay CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 30, 714 31

Abstract:

Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A controller provides the arm command and issues appropriate configuration controls to collect signal samples. In particular, a network responds to these commands from the controller to selectively provide signal samples from a device under test. A trigger event generator responds to logic or other characteristics of the signal samples to provide trigger events. These trigger events are counted by a trigger event counter in the armed state of the state machine to identify the final trigger event corresponding to an occurrence of a programmable number of the trigger events. A store event generator also responds to a programmed characteristic or combination(s) of the signal samples to provide a store event. Either or both of the event generators may use a mask to provide these events.

US Patent:

7480590, Jan 20, 2009

Filed:

Jun 9, 2004

Appl. No.:

10/863256

Inventors:

Jeffrey C. Swanson - Sunnyvale CA, US
John A. Wickeraad - Granite Bay CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 7/42
G06F 7/00

US Classification:

702182, 702189, 702117

Abstract:

A performance adder for providing a running total of performance values within an integrated circuit chip. The performance adder is triggered by various performance events as determined through multiplexer logic for detecting occurrence of a particular performance event. The multiplexer logic can also trigger the performance adder through atomic, edge, toggle, or on/off signals related to the performance events or through a logical function of a combination of performance events. The performance adders can be used to compute average latency of a component in the circuit.